Abstract: Improved means and methods for controlling the sequencing and branching of microinstructions in a microprogrammed digital data processing system. Microinstructions are stored without replication in a programmable read-only control memory and corresponding microinstruction addresses and associated test select bits are stored in a separate programmable read-only memory having an instruction address storage capacity which is a predetermined multiple of the number of microinstructions in the control memory depending upon the branching capability desired. A common address register is used for both of the control and address memories, the remaining portion of the control memory addressing being derived from testing particular system conditions selected by test select signals obtained from the address memory.

Abstract: Longitudinal parity is continuously provided for a predetermined plurality of words stored in a digital memory in a simple and expeditious manner without interfering with normal memory operation. The outputs of the memory read and write registers are applied in corresponding bit pairs to respective ones of a plurality of Exclusive ORs whose outputs are employed to update the respective flip flops of a longitudinal parity register at a time which is specially chosen so that the old word read out of the memory and the new word to be written therein are simultaneously available in the read and write registers.