Abstract: A nanoparticle comprises water-insoluble polymer matrix and an indicator constituent(s), wherein the indicator constituent(s) is released from the nanoparticle only when the polymer matrix is degraded or broken, and then an indicative effect is triggered or enhanced. A nanoparticle-based method for screening a bioactive substance and a microfluidic-based screening system have also been disclosed.

Abstract: A nanoparticle comprises water-insoluble polymer matrix and an indicator constituent(s), wherein the indicator constituent(s) is released from the nanoparticle only when the polymer matrix is degraded or broken, and then an indicative effect is triggered or enhanced. A nanoparticle-based method for screening a bioactive substance and a microfluidic-based screening system have also been disclosed.

Abstract: A signal path linearizer for PAM4 SerDes communications compensates (including pre-compensates) for signal path nonlinearities. The linearizer can be configured with first and second differential gm stages, the first differential gm stage to provide a DC gain, and the second differential gm stage to introduce a defined nonlinear adjustment in DC gain by adding to or subtracting from the DC gain of the first differential gm stage. The differential gm stages can be configured to generate a compensated PAM4 signal with the combined DC gain providing a nonlinear wideband gain adjustment to compensate for nonlinearities in the PAM4 signal path. Compensation range can be increased by selective degeneration, and the compensation region can be shifted by selectively introducing input offset(s).

Abstract: A signal path linearizer for PAM4 SerDes communications compensates (including pre-compensates) for signal path nonlinearities. The linearizer can be configured with first and second differential gm stages, the first differential gm stage to provide a DC gain, and the second differential gm stage to introduce a defined nonlinear adjustment in DC gain by adding to or subtracting from the DC gain of the first differential gm stage. The differential gm stages can be configured to generate a compensated PAM4 signal with the combined DC gain providing a nonlinear wideband gain adjustment to compensate for nonlinearities in the PAM4 signal path. Compensation range can be increased by selective degeneration, and the compensation region can be shifted by selectively introducing input offset(s).

Abstract: An equalizer, in at least some embodiments, comprises an amplifier configured to produce an amplified voltage signal that is a function of an ambient temperature affecting the equalizer. The equalizer also includes a linear equalizer stage coupled to the amplifier and comprising a transistor having a resistance controlled by the amplified voltage signal. The linear equalizer stage is configured to produce a voltage output signal having a gain that is dependent on the transistor resistance and on a frequency of the amplified voltage signal.

Abstract: An equalizer, in at least some embodiments, comprises an amplifier configured to produce an amplified voltage signal that is a function of an ambient temperature affecting the equalizer. The equalizer also includes a linear equalizer stage coupled to the amplifier and comprising a transistor having a resistance controlled by the amplified voltage signal. The linear equalizer stage is configured to produce a voltage output signal having a gain that is dependent on the transistor resistance and on a frequency of the amplified voltage signal.

Abstract: Continuous time sigma delta (??) analog-to-digital conversion (ADC) circuitry and method in which current mode ?? ADC circuitry is driven directly by current mode mixing circuitry, thereby avoiding a need for a current-to-voltage driver between the input signal mixing circuitry and ?? ADC circuitry.

Abstract: Continuous time sigma delta (??) analog-to-digital conversion (ADC) circuitry and method in which current mode ?? ADC circuitry is driven directly by current mode mixing circuitry, thereby avoiding a need for a current-to-voltage driver between the input signal mixing circuitry and ?? ADC circuitry.

Abstract: A signal generator for use in producing a video top-of-frame signal based upon an input video signal with an input video frame including one or more input video fields and having an input video frame rate for an output video signal with an output video frame having a plurality of output video frame lines, each with a plurality of output video pixels, and an output video frame rate.

Abstract: An integrated video clock signal generator in which a master phase-locked loop (PLL) control circuit uses an off-chip voltage-controlled oscillator (VCO) to produce an on-chip oscillator signal in synchronization with a horizontal reference signal related to a horizontal video synchronization signal. This on-chip oscillator signal drives one or more slave PLL circuits which provide respective one or more on-chip PLL signals synchronized with the on-chip oscillator signal. In accordance with a preferred embodiment, each on-chip PLL signal is a pixel clock signal with a plurality of clock signal pulses which is synchronized with a vertical reference signal related to a vertical video synchronization signal.

Abstract: An integrated video clock signal generator in which a master phase-locked loop (PLL) control circuit uses an off-chip voltage-controlled oscillator (VCO) to produce an on-chip oscillator signal in synchronization with a horizontal reference signal related to a horizontal video synchronization signal. This on-chip oscillator signal drives one or more slave PLL circuits which provide respective one or more on-chip PLL signals synchronized with the on-chip oscillator signal. In accordance with a preferred embodiment, each on-chip PLL signal is a pixel clock signal with a plurality of clock signal pulses which is synchronized with a vertical reference signal related to a vertical video synchronization signal.

Abstract: A signal generator for use in producing a video top-of-frame signal based upon an input video signal with an input video frame including one or more input video fields and having an input video frame rate for an output video signal with an output video frame having a plurality of output video frame lines, each with a plurality of output video pixels, and an output video frame rate.

Abstract: A signal detector for detecting and indicating the duration of a signal pulse by comparing the relative polarities of two voltages generated during the two states of the pulsed signal.

Abstract: A video signal mode detector for automatically detecting and indicating the type of video signal being received in terms of its video signal characteristics, including horizontal line count and progressive or interlaced scanning.

Abstract: A video synchronization signal detector for detecting occurrences of single and double frequency synchronization signal pulses present during a vertical synchronization interval.

Abstract: A video synchronization signal removal circuit in which a synchronization signal component of an incoming video signal is detected whereupon a reference signal corresponding to a black video level is substituted substantially during the synchronization signal interval.

Abstract: A circuit and method for clamping a composite video component signal at the video black level by using horizontal synchronization timing information contained within the signal and clamping the signal during a time interval in which it is at the desired black level.

Abstract: Apparatus and method for converting a Y-Pb-Pr component video signal to a R-G-B component video signal. A luminance component video (Y) signal and a red color difference component video (Pr) signal are decoded to produce a red component video (R) signal. The Y signal, a blue color difference component video (Pb) signal and the Pr signal are decoded to produce a green component video (G) signal. The Y and Pb signals are decoded to produce a blue component video (B) signal.

Abstract: A video synchronization signal detector for detecting occurrences of single and double frequency synchronization signal pulses present during a vertical synchronization interval.

Abstract: A video signal mode detector for automatically detecting and indicating the type of video signal being received in terms of its video signal characteristics, including horizontal line count and progressive or interlaced scanning.