Abstract: Certain aspects of the present disclosure provide apparatus and techniques to generate signals for clock spur attenuation. An example apparatus generally includes: one or more circuits coupled between a voltage rail and a reference potential node, wherein the one or more circuits are configured to operate using a clock signal; a delay signal generator configured to receive the clock signal and apply a delay to the clock signal to generate a delay signal; and signal generation circuitry coupled between the voltage rail and the reference potential node and configured to generate a signal fluctuation on at least one of the voltage rail or the reference potential node based on the delay signal.

Abstract: An electronic device includes: a communication circuit; a display; at least one processor including processing circuitry; and memory storing instructions that, when executed by the at least one processor individually or collectively, cause the electronic device to: display a lock screen for user authentication through the display based on an event for subscriber identity module (SIM) authentication being generated, acquire a personal identification number (PIN) for an SIM unlock based on acquisition of user authentication information for releasing the lock screen, identify whether the acquired PIN corresponds to a stored PIN, and perform the SIM unlock, based on identifying that the acquired PIN corresponds to the stored PIN.

Abstract: Methods and apparatus for wireless communication using a transmitter capable of digital predistortion (DPD) and having a main signal path separated from a predistortion signal path, each path including a digital-to-analog converter (DAC). An example apparatus generally includes a main signal path comprising a first DAC, a power amplifier, and a combiner, the combiner being disposed in the main signal path between an output of the first DAC and an input of the power amplifier. The apparatus also includes a predistortion signal path comprising a second DAC, wherein the combiner is configured to combine a predistortion signal in the predistortion signal path with a main signal in the main signal path.

Abstract: A duty cycle correction circuit includes four pairs of serially coupled transistors. A first two of the serial pairs of transistors couple between an internal node for complement output clock signal and ground. A second two of the serial pairs of transistors couple between the internal node and a power supply node for a power supply voltage. Each serial pair is controlled by a corresponding pair of quadrature clock signals in which one of the quadrature clock signal is delayed with respect to the other quadrature clock signal be one quarter of a clock period. The first two serial pairs of transistors thus combine to discharge the internal node for one-half clock period whereas the second two serial pairs of transistors combine to charge the internal node for one-half clock period so that the complement output clock signal has a 50% duty cycle.

Abstract: Methods and apparatus for sharing digital-to-analog (DAC) converters in a reconfigurable DAC circuit to support two or more transmit chains of a wireless transmitter configured for different radio access technologies (RATs) and/or different transmitter architectures. One example DAC circuit generally includes at least four DACs and a plurality of switches coupled to outputs of the at least four DACs such that the DAC circuit is configured as a multi-channel DAC circuit with at least four channels for a first set of one or more frequency bands and as an interleaved DAC circuit with at least two channels for a second set of one or more frequency bands different from the first set of frequency bands.

Abstract: Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) circuit. The DAC circuit generally includes: a decoder coupled to an input of the DAC circuit and current-steering cells coupled to an output of the decoder. Outputs of the current-steering cells may be coupled to a positive output node and a negative output node of the DAC circuit. The DAC circuit may also include an offset detection circuit including: a comparator having a first input and a second input selectively coupled to the positive output node and the negative output node; and a digital controller having an input coupled to an output of the comparator and an output coupled to the decoder. In some aspects, the DAC circuit includes one or more calibration DACs coupled to the offset detection circuit.

Abstract: An electronic device may obtain a security rule for supporting split tunneling, check a condition for executing a first operation related to bypassing the VPN tunnel by comparing a first value to information based on a first offset in a first element of the packet based on the security rule, check a condition for performing a second operation related to bypassing the VPN tunnel by comparing a second value to information based on a second offset in a second element of the packet when the condition for executing the first operation is satisfied and the first operation instructs that the second element of the packet be inspected, encapsulate the packet while not including the packet in the VPN tunnel and transmit the encapsulated packet to a packet forwarding server, and include the packet in the VPN tunnel and transmit the packet to the packet forwarding server.

Abstract: Certain aspects of the present disclosure provide apparatus and techniques to generate signals for clock spur attenuation. An example apparatus generally includes: one or more circuits coupled between a voltage rail and a reference potential node, wherein the one or more circuits are configured to operate using a clock signal; a delay signal generator configured to receive the clock signal and apply a delay to the clock signal to generate a delay signal; and signal generation circuitry coupled between the voltage rail and the reference potential node and configured to generate a signal fluctuation on at least one of the voltage rail or the reference potential node based on the delay signal.

Abstract: Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) circuit. The DAC circuit generally includes: a decoder coupled to an input of the DAC circuit and current-steering cells coupled to an output of the decoder. Outputs of the current-steering cells may be coupled to a positive output node and a negative output node of the DAC circuit. The DAC circuit may also include an offset detection circuit including: a comparator having a first input and a second input selectively coupled to the positive output node and the negative output node; and a digital controller having an input coupled to an output of the comparator and an output coupled to the decoder. In some aspects, the DAC circuit includes one or more calibration DACs coupled to the offset detection circuit.

Abstract: A duty cycle correction circuit includes four pairs of serially coupled transistors. A first two of the serial pairs of transistors couple between an internal node for complement output clock signal and ground. A second two of the serial pairs of transistors couple between the internal node and a power supply node for a power supply voltage. Each serial pair is controlled by a corresponding pair of quadrature clock signals in which one of the quadrature clock signal is delayed with respect to the other quadrature clock signal be one quarter of a clock period. The first two serial pairs of transistors thus combine to discharge the internal node for one-half clock period whereas the second two serial pairs of transistors combine to charge the internal node for one-half clock period so that the complement output clock signal has a 50% duty cycle.

Abstract: An electronic device according to an embodiment includes a memory storing instructions, a global positioning system (GPS) receiver, a communication circuit, and a processor. The processor, when executing the instructions, is configured to establish a connection with a public access point (AP) to communicate with an external electronic device, obtain location information of the electronic device, maintain a state of mode for a VPN in an inactive state, based on transmitting information distinct from the location information, on a condition that the number of a plurality of electronic devices located within a reference distance from the public AP is less than a reference value, and switch the state of mode for VPN mode from the inactive state to an active state, based on transmitting the information on a condition that the number of the plurality of electronic devices is equal to or greater than the reference value.

Abstract: Methods and apparatus for sharing digital-to-analog (DAC) converters in a reconfigurable DAC circuit to support two or more transmit chains of a wireless transmitter configured for different radio access technologies (RATs) and/or different transmitter architectures. One example DAC circuit generally includes at least four DACs and a plurality of switches coupled to outputs of the at least four DACs such that the DAC circuit is configured as a multi-channel DAC circuit with at least four channels for a first set of one or more frequency bands and as an interleaved DAC circuit with at least two channels for a second set of one or more frequency bands different from the first set of frequency bands.

Abstract: Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current steering cells, each comprising a current source coupled to at least two current steering switches, wherein control inputs of the at least two current steering switches are coupled to an input path of the DAC system. The DAC system may also include a current source toggle circuit configured to selectively disable the current source of at least one of the plurality of current steering cells, and a feedforward path coupled between the input path and at least one control input of the current source toggle circuit.

Abstract: Methods and apparatus for adaptively generating a reference voltage (VREF) for biasing a switch driver and corresponding switch in a digital-to-analog converter (DAC). The adaptive biasing scheme may be capable of tracking process, voltage, and temperature (PVT) of the DAC. An example DAC generally includes a plurality of DAC cells, each DAC cell comprising a current source, a switch coupled in series with the current source, and a switch driver coupled to a control input of the switch, the switch driver being configured to receive power from a first power supply rail referenced to a reference potential node; a regulation circuit comprising a first transistor coupled between the reference potential node for the DAC and the switch driver in at least one of the plurality of DAC cells; and a VREF generation circuit coupled to the regulation circuit and configured to adaptively generate a VREF for the regulation circuit.

Abstract: An electronic device may obtain a security rule for supporting split tunneling, check a condition for executing a first operation related to bypassing the VPN tunnel by comparing a first value to information based on a first offset in a first element of the packet based on the security rule, check a condition for performing a second operation related to bypassing the VPN tunnel by comparing a second value to information based on a second offset in a second element of the packet when the condition for executing the first operation is satisfied and the first operation instructs that the second element of the packet be inspected, encapsulate the packet while not including the packet in the VPN tunnel and transmit the encapsulated packet to a packet forwarding server, and include the packet in the VPN tunnel and transmit the packet to the packet forwarding server.

Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example device for digital-to-analog conversion generally includes: a digital-to-analog converter (DAC) having an input coupled to an input node of the device; a first return-to-zero (RZ) DAC having an input coupled to an input node of the device; and a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the first RZ DAC is coupled to a second input of the combiner.

Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example device for digital-to-analog conversion generally includes: a digital-to-analog converter (DAC) having an input coupled to an input node of the device; a first return-to-zero (RZ) DAC having an input coupled to an input node of the device; and a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the first RZ DAC is coupled to a second input of the combiner.

Abstract: An electronic device according to an embodiment includes a memory storing instructions, a global positioning system (GPS) receiver, a communication circuit, and a processor. The processor, when executing the instructions, is configured to establish a connection with a public access point (AP) to communicate with an external electronic device, obtain location information of the electronic device, maintain a state of mode for a VPN in an inactive state, based on transmitting information distinct from the location information, on a condition that the number of a plurality of electronic devices located within a reference distance from the public AP is less than a reference value, and switch the state of mode for VPN mode from the inactive state to an active state, based on transmitting the information on a condition that the number of the plurality of electronic devices is equal to or greater than the reference value.

Abstract: Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current steering cells, each comprising a current source coupled to at least two current steering switches, wherein control inputs of the at least two current steering switches are coupled to an input path of the DAC system. The DAC system may also include a current source toggle circuit configured to selectively disable the current source of at least one of the plurality of current steering cells, and a feedforward path coupled between the input path and at least one control input of the current source toggle circuit.

Abstract: Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current sources, a plurality of calibration DACs, each coupled to a respective one of the plurality of current sources, a reference current source, and a current mirror having a first branch selectively coupled to the plurality of current sources, wherein a second branch of the current mirror is coupled to the reference current source. The DAC system also includes a first error DAC selectively coupled to the first branch and the second branch of the current mirror, and a second error DAC selectively coupled to the first branch and the second branch of the current mirror.