Patents by Inventor Dongxiang Liao
Dongxiang Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20180373644Abstract: Apparatuses, systems, methods, and computer program products are disclosed for multi-plane memory management. An apparatus includes a failure detection circuit that detects a failure of a storage element during an operation. An apparatus includes a test circuit that performs a test on a storage element. An apparatus includes a recycle circuit that enables a portion of a storage element for use in operations in response to the portion of the storage element passing a test.Type: ApplicationFiled: June 26, 2017Publication date: December 27, 2018Applicant: Western Digital Technologies, Inc.Inventors: Daniel Joseph Linnen, Ashish Ghai, Dongxiang Liao, Srikar Peesari, Avinash Rajagiri, Philip Reusswig, Bin Wu
-
Publication number: 20180350445Abstract: Techniques are presented for testing the high-speed data path between the IO pads and the read/write buffer of a memory circuit without the use of an external test device. In an on-chip process, a data test pattern is transferred at a high data rate between the read/write register and a source for the test pattern, such as register for this purpose or the read/write buffer of another plane. The test data after the high-speed transfer is then checked against its expected, uncorrupted value, such as by transferring it back at a lower speed for comparison or by transferring the test data a second time, but at a lower rate, and comparing the high transfer rate copy with the lower transfer rate copy at the receiving end of the transfers.Type: ApplicationFiled: May 31, 2017Publication date: December 6, 2018Applicant: SANDISK TECHNOLOGIES LLCInventors: Daniel Linnen, Srikar Peesari, Kirubakaran Periyannan, Shantanu Gupta, Avinash Rajagiri, Dongxiang Liao, Jagdish Sabde, Rajan Paudel
-
Patent number: 10147877Abstract: In fabricating a memory device, a first electrode is provided. An oxide layer is provided on the first electrode. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. An oxide layer is provided on the first electrode, the oxide layer comprising an oxygen deficiency and/or defects therein. A second electrode is then provided on the oxide layer.Type: GrantFiled: September 7, 2016Date of Patent: December 4, 2018Assignee: Cypress Semiconductor CorporationInventors: Matthew Buynoski, Seungmoo Choi, Chakravarthy Gopalan, Dongxiang Liao, Christie Marrian
-
Publication number: 20160380195Abstract: In fabricating a memory device, a first electrode is provided. An oxide layer is provided on the first electrode. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. An oxide layer is provided on the first electrode, the oxide layer comprising an oxygen deficiency and/or defects therein. A second electrode is then provided on the oxide layer.Type: ApplicationFiled: September 7, 2016Publication date: December 29, 2016Inventors: Matthew BUYNOSKI, Seungmoo Choi, Chakravarthy Gopalan, Dongxiang Liao, Christie Marrian
-
Patent number: 9461247Abstract: In fabricating a memory device, a first electrode is provided. An alloy is formed thereon, and the alloy is oxidized to provide an oxide layer. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. Oxide is provided on the first electrode, and an implantation step in undertaken to implant material in the oxide to form a layer including oxide and implanted material having an oxygen deficiency and/or defects therein. A second electrode is then formed on the layer.Type: GrantFiled: February 2, 2015Date of Patent: October 4, 2016Assignee: Cypress Semiconductor CorporationInventors: Matthew Buynoski, Seungmoo Choi, Chakravarthy Gopalan, Dongxiang Liao, Christie Marrian
-
Publication number: 20150144857Abstract: In fabricating a memory device, a first electrode is provided. An alloy is formed thereon, and the alloy is oxidized to provide an oxide layer. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. Oxide is provided on the first electrode, and an implantation step in undertaken to implant material in the oxide to form a layer including oxide and implanted material having an oxygen deficiency and/or defects therein. A second electrode is the formed on the layer.Type: ApplicationFiled: February 2, 2015Publication date: May 28, 2015Inventors: Matthew BUYNOSKI, Seungmoo CHOI, Chakravarthy GOPALAN, Dongxiang LIAO, Christie MARRIAN
-
Patent number: 8946020Abstract: In fabricating a memory device, a first electrode is provided. An alloy is formed thereon, and the alloy is oxidized to provide an oxide layer. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. Oxide is provided on the first electrode, and an implantation step in undertaken to implant material in the oxide to form a layer including oxide and implanted material having an oxygen deficiency and/or defects therein. A second electrode is then formed on the layer.Type: GrantFiled: September 6, 2007Date of Patent: February 3, 2015Assignee: Spansion, LLCInventors: Matthew Buynoski, Seungmoo Choi, Chakravarthy Gopalan, Dongxiang Liao, Christie Marrian
-
Patent number: 8828837Abstract: In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.Type: GrantFiled: April 19, 2013Date of Patent: September 9, 2014Assignee: Spansion LLCInventors: Steven Avanzino, Tzu-Ning Fang, Swaroop Kaza, Dongxiang Liao, Wai Lo, Christie Marrian, Sameer Haddad
-
Publication number: 20130237030Abstract: In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.Type: ApplicationFiled: April 19, 2013Publication date: September 12, 2013Applicant: Spansion LLCInventors: Steven AVANZINO, Tzu-Ning FANG, Swaroop KAZA, Dongxiang LIAO, Wai LO, Christie MARRIAN, Sameer HADDAD
-
Patent number: 8445913Abstract: In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.Type: GrantFiled: October 30, 2007Date of Patent: May 21, 2013Assignee: Spansion LLCInventors: Steven Avanzino, Tzu-Ning Fang, Swaroop Kaza, Dongxiang Liao, Wai Lo, Christie Marrian, Sameer Haddad
-
Publication number: 20120017415Abstract: A method for using a reusable sample-holding device for readily loading very small wet samples for observation of the samples by microscopic equipment, in particular in a vacuum environment. The method may be used with a scanning electron microscope (SEM), a transmission electron microscope (TEM), an X-ray microscope, optical microscope, and the like. For observation of the sample, the method provides a thin-membrane window etched in the center of each of two silicon wafers abutting to contain the sample in a small uniform gap formed between the windows. This gap may be adjusted by employing spacers. Alternatively, the thickness of a film established by the fluid in which the sample is incorporated determines the gap without need of a spacer. To optimize resolution each window may have a thickness on the order of 50 nm and the gap may be on the order of 50 nm.Type: ApplicationFiled: September 22, 2011Publication date: January 26, 2012Inventors: Charles P. MARSH, Eric OLSON, Todor I. DONCHEV, Ivan PETROV, Jianguo WEN, Ryan FRANKS, Dongxiang LIAO
-
Patent number: 8102523Abstract: A method for using a reusable sample-holding device for readily loading very small wet samples for observation of the samples by microscopic equipment, in particular in a vacuum environment. The method may be used with a scanning electron microscope (SEM), a transmission electron microscope (TEM), an X-ray microscope, optical microscope, and the like. For observation of the sample, the method provides a thin-membrane window etched in the center of each of two silicon wafers abutting to contain the sample in a small uniform gap formed between the windows. This gap may be adjusted by employing spacers. Alternatively, the thickness of a film established by the fluid in which the sample is incorporated determines the gap without need of a spacer. To optimize resolution each window may have a thickness on the order of 50 nm and the gap may be on the order of 50 nm.Type: GrantFiled: September 22, 2011Date of Patent: January 24, 2012Assignee: The United States of America as represented by the Secretary of the ArmyInventors: Charles P. Marsh, Eric Olson, Todor I. Donchev, Ivan Petrov, Jianguo Wen, Ryan Franks, Dongxiang Liao
-
Patent number: 8059271Abstract: A reusable sample-holding device for readily loading very small wet samples for observation of the samples by microscopic equipment, in particular in a vacuum environment. Embodiments may be used with a scanning electron microscope (SEM), a transmission electron microscope (TEM), an X-ray microscope, optical microscope, and the like. For observation of the sample, embodiments provide a thin-membrane window etched in the center of each of two silicon wafers abutting to contain the sample in a small uniform gap formed between the windows. This gap may be adjusted by employing spacers. Alternatively, the thickness of a film established by the fluid in which the sample is incorporated determines the gap without need of a spacer. To optimize resolution each window may have a thickness on the order of 50 nm and the gap may be on the order of 50 nm.Type: GrantFiled: February 4, 2009Date of Patent: November 15, 2011Assignee: The United States of America as represented by the Secretary of the ArmyInventors: Charles P. Marsh, Eric Olson, Todor I. Donchev, Ivan Petrov, Jianguo Wen, Ryan Franks, Dongxiang Liao
-
Publication number: 20100193398Abstract: A reusable sample-holding device for readily loading very small wet samples for observation of the samples by microscopic equipment, in particular in a vacuum environment. Embodiments may be used with a scanning electron microscope (SEM), a transmission electron microscope (TEM), an X-ray microscope, optical microscope, and the like. For observation of the sample, embodiments provide a thin-membrane window etched in the center of each of two silicon wafers abutting to contain the sample in a small uniform gap formed between the windows. This gap may be adjusted by employing spacers. Alternatively, the thickness of a film established by the fluid in which the sample is incorporated determines the gap without need of a spacer. To optimize resolution each window may have a thickness on the order of 50 nm and the gap may be on the order of 50 nm.Type: ApplicationFiled: February 4, 2009Publication date: August 5, 2010Inventors: CHARLES P. MARSH, ERIC OLSON, TODOR I. DONCHEV, IVAN PETROV, JIANGUO WEN, RYAN FRANKS, DONGXIANG LIAO
-
Patent number: 7706168Abstract: The present method provides annealing of a resistive memory device so as to provide that the device in its erased state has a greatly increased resistance as compared to a prior art approach. The annealing also provides that the device may be erased by application of any of a plurality of electrical potentials within an increased range of electrical potentials as compared to the prior art.Type: GrantFiled: October 30, 2007Date of Patent: April 27, 2010Assignee: Spansion LLCInventors: Tzu-Ning Fang, Steven Avanzino, Swaroop Kaza, Dongxiang Liao, Christie Marrian, Sameer Haddad
-
Patent number: 7566628Abstract: Methods of making MIM structures and the resultant MIM structures are provided. The method involves forming a top electrode layer over a bottom electrode and an insulator on a substrate and forming a top electrode by removing portions of the top electrode layer. The bottom electrode, insulator, or combination thereof is isolated from the top electrode forming process, thereby mitigating damage to the resultant metal-insulator-metal structure. The resultant MIM structure can be a portion of a resistive memory cell.Type: GrantFiled: June 15, 2007Date of Patent: July 28, 2009Assignee: Spansion LLCInventors: Dongxiang Liao, Suzette K. Pangrle, Chakku Gopalan
-
Publication number: 20090109598Abstract: In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.Type: ApplicationFiled: October 30, 2007Publication date: April 30, 2009Inventors: Steven Avanzino, Tzu-Ning Fang, Swaroop Kaza, Dongxiang Liao, Wai Lo, Christie Marrian, Sameer Haddad
-
Publication number: 20090109727Abstract: The present method provides annealing of a resistive memory device so as to provide that the device in its erased state has a greatly increased resistance as compared to a prior art approach. The annealing also provides that the device may be erased by application of any of a plurality of electrical potentials within an increased range of electrical potentials as compared to the prior art.Type: ApplicationFiled: October 30, 2007Publication date: April 30, 2009Inventors: Tzu-Ning Fang, Steven Avanzino, Swaroop Kaza, Dongxiang Liao, Christie Marrian, Sameer Haddad
-
Publication number: 20090067213Abstract: In fabricating a memory device, a first electrode is provided. An alloy is formed thereon, and the alloy is oxidized to provide an oxide layer. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. Oxide is provided on the first electrode, and an implantation step in undertaken to implant material in the oxide to form a layer including oxide and implanted material having an oxygen deficiency and/or defects therein. A second electrode is then formed on the layer.Type: ApplicationFiled: September 6, 2007Publication date: March 12, 2009Inventors: Matthew Buynoski, Seungmoo Choi, Chakravarthy Gopalan, Dongxiang Liao, Christie Marrian
-
Publication number: 20080308781Abstract: Methods of making MIM structures and the resultant MIM structures are provided. The method involves forming a top electrode layer over a bottom electrode and an insulator on a substrate and forming a top electrode by removing portions of the top electrode layer. The bottom electrode, insulator, or combination thereof is isolated from the top electrode forming process, thereby mitigating damage to the resultant metal-insulator-metal structure. The resultant MIM structure can be a portion of a resistive memory cell.Type: ApplicationFiled: June 15, 2007Publication date: December 18, 2008Applicant: SPANSION LLCInventors: Dongxiang Liao, Suzette K. Pangrle, Chakku Gopalan