Patents by Inventor Dongxiang Luo

Dongxiang Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9960260
    Abstract: A Metal Oxide Thin Film Transistor (MOTFT) and a preparation method thereof are provided. The preparation method includes the following steps in turn: Step a: a metal conductive layer is prepared and patterned as a gate on a substrate; Step b: a first insulating thin film is deposited as a gate insulating layer on the metal conductive layer; Step c: a metal oxide thin film is deposited and patterned as an active layer on the gate insulating layer; Step d: an organic conductive thin film is deposited as a back channel etch protective layer on the active layer; Step e: a metal layer is deposited on the back channel etch protective layer and then patterned as pattern of a source electrode and a drain electrode; Step f: a second insulating thin film is deposited as a passivation layer on the source electrode and the drain electrode.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: May 1, 2018
    Assignee: Guang Zhou New Vision Opto-Electronic Technology Co., Ltd.
    Inventors: Miao Xu, Dongxiang Luo, Hongmeng Li, Jiawei Pang, Ying Guo, Lang Wang
  • Publication number: 20160133729
    Abstract: A Metal Oxide Thin Film Transistor (MOTFT) and a preparation method thereof are provided. The preparation method includes the following steps in turn: Step a: a metal conductive layer is prepared and patterned as a gate on a substrate; Step b: a first insulating thin film is deposited as a gate insulating layer on the metal conductive layer; Step c: a metal oxide thin film is deposited and patterned as an active layer on the gate insulating layer; Step d: an organic conductive thin film is deposited as a back channel etch protective layer on the active layer; Step e: a metal layer is deposited on the back channel etch protective layer and then patterned as pattern of a source electrode and a drain electrode; Step f: a second insulating thin film is deposited as a passivation layer on the source electrode and the drain electrode.
    Type: Application
    Filed: August 7, 2013
    Publication date: May 12, 2016
    Inventors: Miao XU, Dongxiang LUO, Hongmeng LI, Jiawei PANG, Ying GUO, Lang WANG
  • Patent number: 7777540
    Abstract: The present invention discloses a PLL, a lock detector thereof and a lock detection method. The lock detector includes: a first detecting unit, adapted to compare a counting value of a reference clock signal with a counting value of a feedback clock signal every first interval and output a valid first prelock signal when the counting value of the reference clock signal is equal to the counting value of the feedback clock signal; a second detecting unit, adapted to output a valid second prelock signal when the counting value of the reference clock signal is equal to the counting value of the feedback clock signal during a second interval which is at least two times higher than the first interval; a third detecting unit, adapted to output a valid lock signal if the first prelock signal output from the first detecting unit every first interval is valid and the second prelock signal output from the second detecting unit is valid during the second interval.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: August 17, 2010
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Jinzhong Peng, Zhigang Fu, Juncheng Wang, Dongxiang Luo, Qinglong Lin
  • Publication number: 20100039151
    Abstract: The present invention discloses a PLL, a lock detector thereof and a lock detection method. The lock detector includes: a first detecting unit, adapted to compare a counting value of a reference clock signal with a counting value of a feedback clock signal every first interval and output a valid first prelock signal when the counting value of the reference clock signal is equal to the counting value of the feedback clock signal; a second detecting unit, adapted to output a valid second prelock signal when the counting value of the reference clock signal is equal to the counting value of the feedback clock signal during a second interval which is at least two times higher than the first interval; a third detecting unit, adapted to output a valid lock signal if the first prelock signal output from the first detecting unit every first interval is valid and the second prelock signal output from the second detecting unit is valid during the second interval.
    Type: Application
    Filed: February 20, 2009
    Publication date: February 18, 2010
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Jinzhong PENG, Zhigang FU, Juncheng WANG, Dongxiang LUO, Qinglong LIN