Abstract: An integrated circuit includes two N wells from two different devices in close proximity to each other with each N well biased by two different terminals. The N wells are at least partially surrounded by P type regions that are biased by a terminal. The integrated circuit includes conductivity reduction features that increase the resistivity of current paths to a P type regions of one device on a side closest the other device. The integrated circuit includes two conductive tie biasing structures each located directly over an N type region of the substrate and directly over a P type region of the substrate. The two conductive tie biasing structures are not electrically connected to each other and are not electrically coupled to each other by a conductive biasing structure.

Abstract: As disclosed herein, an integrated circuit substrate includes a first region coupled to a signal terminal and includes a guard region coupled via a diode circuit to a supply voltage terminal of the integrated circuit. The first region and the guard region are both of a first conductivity type. A cathode of the diode circuit is connected to the guard region and an anode of the diode circuit is connected to the supply voltage terminal. The first region and the guard region are separated by at least by a second region of the substrate that is of a second conductivity type opposite the first conductivity type.

Abstract: The disclosure relates to a switched capacitor converter (SCC) with gate driving circuits for limiting currents provided by switching field effect transistors. Embodiments disclosed include an SCC with gate driver curcuits providing gate voltage signals to power FETs, each gate driver circuit comprising first and second gate driver modules and configured to operate in: a first mode in which the first gate driver module provides a gate voltage signal to a power FET that switches between first and second voltage rails by operation of first and second switches connected between the pair of voltage rails; and a second mode in which, in reponse to enabling of a current limit switching signal, the first gate driver module disables switching of one of the first and second switches and the second gate driver module operates to limit a current provided to the power FET.

Abstract: The disclosure relates to a switched capacitor converter with gate driving circuits for limiting currents provided by switching field effect transistors.

Abstract: An integrated circuit includes two N wells from two different devices in close proximity to each other with each N well biased by two different terminals. The N wells are at least partially surrounded by P type regions that are biased by a terminal. The integrated circuit includes conductivity reduction features that increase the resistivity of current paths to a P type regions of one device on a side closest the other device. The integrated circuit includes two conductive tie biasing structures each located directly over an N type region of the substrate and directly over a P type region of the substrate. The two conductive tie biasing structures are not electrically connected to each other and are not electrically coupled to each other by a conductive biasing structure.

Abstract: As disclosed herein, an integrated circuit substrate includes a first region coupled to a signal terminal and includes a guard region coupled via a diode circuit to a supply voltage terminal of the integrated circuit. The first region and the guard region are both of a first conductivity type. A cathode of the diode circuit is connected to the guard region and an anode of the diode circuit is connected to the supply voltage terminal. The first region and the guard region are separated by at least by a second region of the substrate that is of a second conductivity type opposite the first conductivity type.

Abstract: Gate-protection circuitry protects a transistor, such as a MOSFET, from large gate-to-source voltage differentials that can permanently damage the transistor's gate-oxide layer. A source-voltage detector selectively enables the gate-protection circuitry based on a source voltage of the transistor. The gate-protection circuit is implemented without any Zener diodes. The transistor may be a load switch that is selectively controlled to apply a supply voltage to a load.

Abstract: Gate-protection circuitry protects a transistor, such as a MOSFET, from large gate-to-source voltage differentials that can permanently damage the transistor's gate-oxide layer. A source-voltage detector selectively enables the gate-protection circuitry based on a source voltage of the transistor. The gate-protection circuit is implemented without any Zener diodes. The transistor may be a load switch that is selectively controlled to apply a supply voltage to a load.

Abstract: A surge protection circuit includes a DC trigger circuit that generates a trigger signal when a surge pulse occurs, and a current conducting unit, coupled to the DC trigger circuit, that generates a first clamp voltage as an output voltage of the surge protection circuit and conducts surge currents to ground in response to the trigger signal. The DC trigger circuit includes a surge detection circuit and a first amplification circuit. The surge detection circuit detects if a surge pulse occurs, and triggers the first amplification circuit to generate the trigger signal when the surge detection circuit detects a surge pulse.

Abstract: A surge protection circuit includes a DC trigger circuit that generates a trigger signal when a surge pulse occurs, and a current conducting unit, coupled to the DC trigger circuit, that generates a first clamp voltage as an output voltage of the surge protection circuit and conducts surge currents to ground in response to the trigger signal. The DC trigger circuit includes a surge detection circuit and a first amplification circuit. The surge detection circuit detects if a surge pulse occurs, and triggers the first amplification circuit to generate the trigger signal when the surge detection circuit detects a surge pulse.

Abstract: A dial testing system and a dial testing method using the dial testing system are provided. The dial testing system includes a dial testing agent device adapted to perform an automatic dial testing through a network element and control an automatic dial testing result reported by the network element; and a dial testing server adapted to collect the automatic dial testing result reported by the dial testing agent device. The dial testing system and the dial testing method provided by the present invention may assure allsidedness of a dial testing, enhance the speed and quality of the dial testing operation, and save a large amount of manpower and material resources.

Abstract: A dial testing system and a dial testing method using the dial testing system are provided. The dial testing system includes a dial testing agent device adapted to perform an automatic dial testing through a network element and control an automatic dial testing result reported by the network element; and a dial testing server adapted to collect the automatic dial testing result reported by the dial testing agent device. The dial testing system and the dial testing method provided by the present invention may assure allsidedness of a dial testing, enhance the speed and quality of the dial testing operation, and save a large amount of manpower and material resources.