Abstract: Examples of the present application disclose semiconductor devices, fabrication methods of semiconductor devices, and semiconductor apparatus. In one example, the semiconductor device includes a first die, the first die includes a first bonding layer, wherein the first bonding layer includes a first connection structure and a first metal ring, the first metal ring disposed around the first connection structure.

Abstract: According to one aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure may include a first wafer. The first wafer may include a plurality of first peripheral circuit chips, a first dicing lane between the first peripheral circuit chips, and a first mark at an edge of the first wafer. A pointing direction of the first mark may be the same as an extending direction of the first dicing lane. A cleavage plane of the first wafer may be parallel to the pointing direction of the first mark. The pointing direction of the first mark may be an extending direction of a line of symmetry of the first wafer. The semiconductor structure may include a second wafer. The second wafer and the first wafer may be disposed in a stack. The second wafer may be a plurality of memory array chips.

Abstract: Examples of the present disclosure disclose a memory and a fabrication method thereof, a memory system, and an electronic device. The memory includes a first semiconductor structure and a second semiconductor structure that are bonded to each other; the first semiconductor structure includes a first dielectric layer and a first conductive pillar located in the first dielectric layer; the second semiconductor structure includes a second dielectric layer and a second conductive pillar located in the second dielectric layer; the second conductive pillar is connected with the first conductive pillar; the memory further includes a heat dissipation channel located in at least one of the first dielectric layer or the second dielectric layer, wherein the heat dissipation channel is disposed as being spaced apart from at least one of the first conductive pillar or the second conductive pillar.

Abstract: A PCR detector is provided, and belongs to the technical field of PCR detection. The PCR detector includes an excitation light source module, a chip device and a detection part; a reaction bin is arranged in an emitting direction of excitation light of the excitation light source module, the detection part is arranged at one side of the reaction bin, and the emitting light formed after the excitation light illuminates the reaction bin can be detected by the detection part, wherein an emitting direction of the excitation light is located below the detection part, and the detection part is configured to detect emitting light emitted by the detected sample in a vertical direction due to the illumination of the excitation light; and the detection part includes a spectrograph, a wavelength scope of a spectrum detected by the spectrograph is 340-850 nm, and the spectrograph can detect the excitation light and the emitting light.

Abstract: Memory device and formation method are provided. The memory device includes a stack structure; and a plurality of gate line slit structures vertically extending through the stack structure to divide the stack structure into a plurality of stack portions. The plurality of GLS structures extend along a first direction in a lateral plane of the stack structure and are arranged along a second direction substantially perpendicular to the first direction. Each stack portion is between corresponding adjacent gate line slit structures. At least one edge stack portion, along the second direction of the plurality of stack portions at edge of the stack structure includes a configuration different from a non-edge stack portion of the plurality of stack portions along the second direction.

Abstract: Three-dimensional (3D) memory devices and fabricating methods are disclosed. A disclosed 3D memory device includes a first semiconductor structure. The first semiconductor structure includes an array of first-type through stack structures in a first region and an array of second-type through stack structures in a second region, and a slit structure separating the array of first-type through stack structures from the array of second-type through stack structures. The 3D memory device further includes a second semiconductor structure. The second semiconductor structure includes a first periphery circuit and a second periphery circuit at different levels. The second semiconductor structure and the first semiconductor structure are bonded together, such that the first periphery circuit is located between the second periphery circuit and the first semiconductor structure.

Abstract: Aspects of the disclosure provide a semiconductor device and a method to manufacture the semiconductor device. A channel hole is formed in a stack including alternating first layers and second layers. The stack is formed over a substrate of the semiconductor device. A gate dielectric layer and a channel layer are sequentially formed in the channel hole. Laser annealing is performed on the channel layer using laser light. An incidence angle of the laser light on an upper surface of the channel layer causes a total internal reflection to occur at an interface between the channel layer and the gate dielectric layer and an interface between the channel layer and an insulating layer that is adjacent to the channel layer.