Patents by Inventor Dongyue Yang
Dongyue Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11675277Abstract: Two pairs of alignment targets (one aligned, one misaligned by a bias distance) are formed on different masks to produce a first pair of conjugated interference patterns. Other pairs of alignment targets are also formed on the masks to produce a second pair of conjugated interference patterns that are inverted the first. Misalignment of the dark and light regions of first interference patterns and the second interference patterns in both pairs of conjugated interference patterns is determined when patterns formed using the masks are overlaid. A magnification factor (of the interference pattern misalignment to the target misalignment) is calculated as a ratio of the difference of misalignment of the relatively dark and relatively light regions in the pairs of interference patterns, over twice the bias distance. The interference pattern misalignment is divided by the magnification factor to produce a self-referenced and self-calibrated target misalignment amount, which is then output.Type: GrantFiled: December 23, 2021Date of Patent: June 13, 2023Assignee: KLA CorporationInventors: Dongyue Yang, Xintuo Dai, Dongsuk Park, Minghao Tang, Md Motasim Bellah, Pavan Kumar Chinthamanipeta Sripadarao, Cheuk Wun Wong
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Publication number: 20220334502Abstract: Two pairs of alignment targets (one aligned, one misaligned by a bias distance) are formed on different masks to produce a first pair of conjugated interference patterns. Other pairs of alignment targets are also formed on the masks to produce a second pair of conjugated interference patterns that are inverted the first. Misalignment of the dark and light regions of first interference patterns and the second interference patterns in both pairs of conjugated interference patterns is determined when patterns formed using the masks are overlaid. A magnification factor (of the interference pattern misalignment to the target misalignment) is calculated as a ratio of the difference of misalignment of the relatively dark and relatively light regions in the pairs of interference patterns, over twice the bias distance. The interference pattern misalignment is divided by the magnification factor to produce a self-referenced and self-calibrated target misalignment amount, which is then output.Type: ApplicationFiled: December 23, 2021Publication date: October 20, 2022Inventors: Dongyue Yang, Xintuo Dai, Dongsuk Park, Minghao Tang, Md Motasim Bellah, Pavan Kumar Chinthamanipeta Sripadarao, Cheuk Wun Wong
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Patent number: 11231654Abstract: Two pairs of alignment targets (one aligned, one misaligned by a bias distance) are formed on different masks to produce a first pair of conjugated interference patterns. Other pairs of alignment targets are also formed on the masks to produce a second pair of conjugated interference patterns that are inverted the first. Misalignment of the dark and light regions of the first interference patterns and the second interference patterns in both pairs of conjugated interference patterns is determined when patterns formed using the masks are overlaid. A magnification factor (of the interference pattern misalignment to the target misalignment) is calculated as a ratio of the difference of misalignment of the relatively dark and relatively light regions in the pairs of interference patterns, over twice the bias distance. The interference pattern misalignment is divided by the magnification factor to produce a self-referenced and self-calibrated target misalignment amount, which is then output.Type: GrantFiled: April 14, 2020Date of Patent: January 25, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Dongyue Yang, Xintuo Dai, Dongsuk Park, Minghao Tang, Md Motasim Bellah, Pavan Kumar Chinthamanipeta Sripadarao, Cheuk Wun Wong
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Patent number: 10833022Abstract: In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.Type: GrantFiled: October 16, 2019Date of Patent: November 10, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Cung D. Tran, Huaxiang Li, Bradley Morgenfeld, Xintuo Dai, Sanggil Bae, Rui Chen, Md Motasim Bellah, Dongyue Yang, Minghao Tang, Christian J. Ayala, Ravi Prakash Srivastava, Kripa Nidhan Chauhan, Pavan Kumar Chinthamanipeta Sripadarao
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Patent number: 10809633Abstract: Structures for detecting and correcting an overlay inaccuracy and methods of detecting and correcting an overlay inaccuracy. An overlay target includes a first plurality of features arranged along a first longitudinal axis in a first line-space pattern having a first line width, and a second plurality of features arranged along a second longitudinal axis in a second line-space pattern having a second line width that is less than the first line width. The second longitudinal axis is aligned substantially parallel to the first longitudinal axis.Type: GrantFiled: September 5, 2019Date of Patent: October 20, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Dongyue Yang, Cheuk Wun Wong, Xintuo Dai, Sanggil Bae
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Patent number: 10733354Abstract: Disclosed are embodiments of a system, method and computer program product for wafer-level design including chip and frame design. The embodiments employ three-dimensional (3D) emulation to preliminarily verify in-kerf optical macros included in a frame design layout. Specifically, 3D images of a given in-kerf optical macro at different process steps are generated by a 3D emulator and a determination is made as to whether or not that macro will be formed as predicted. If not, the plan for the macro is altered using an iterative design process. Once the in-kerf optical macros within the frame design layout have been preliminarily verified, wafer-level design layout verification, including chip and frame design layout verification, is performed. Once the wafer-level design layout has been verified, wafer-level design layout validation, including chip and frame design layout validation, is performed. Optionally, an emulation library can store results of 3D emulation processes for future use.Type: GrantFiled: December 19, 2018Date of Patent: August 4, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Hojin Kim, Dongyue Yang, Dong-Ick Lee, Yue Zhou, Jae Ho Joung, Gregory Costrini, El Mehdi Bazizi, Dongsuk Park
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Publication number: 20200241429Abstract: Two pairs of alignment targets (one aligned, one misaligned by a bias distance) are formed on different masks to produce a first pair of conjugated interference patterns. Other pairs of alignment targets are also formed on the masks to produce a second pair of conjugated interference patterns that are inverted the first. Misalignment of the dark and light regions of the first interference patterns and the second interference patterns in both pairs of conjugated interference patterns is determined when patterns formed using the masks are overlaid. A magnification factor (of the interference pattern misalignment to the target misalignment) is calculated as a ratio of the difference of misalignment of the relatively dark and relatively light regions in the pairs of interference patterns, over twice the bias distance. The interference pattern misalignment is divided by the magnification factor to produce a self-referenced and self-calibrated target misalignment amount, which is then output.Type: ApplicationFiled: April 14, 2020Publication date: July 30, 2020Applicant: GLOBALFOUNDRIES INC.Inventors: Dongyue Yang, Xintuo Dai, Dongsuk Park, Minghao Tang, Md Motasim Bellah, Pavan Kumar Chinthamanipeta Sripadarao, Cheuk Wun Wong
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Patent number: 10707175Abstract: One illustrative example of an overlay mark disclosed herein includes four quadrants (I-IV). Each quadrant of the mark contains an inner periodic structure and an outer periodic structure. Each of the outer periodic structures includes a plurality of outer features. Each of the inner periodic structures includes a plurality of first inner groups, each of the first inner groups having a plurality of first inner features, each first inner group being oriented such that there is an end-to-end spacing relationship between each first inner group and a selected one of the outer features.Type: GrantFiled: May 22, 2018Date of Patent: July 7, 2020Assignee: GLOBALFOUNDRIES Inc.Inventors: Wei Zhao, Minghao Tang, Rui Chen, Dongyue Yang, Haiting Wang, Erik Geiss, Scott Beasor
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Patent number: 10705435Abstract: Two pairs of alignment targets (one aligned, one misaligned by a bias distance) are formed on different masks to produce a first pair of conjugated interference patterns. Other pairs of alignment targets are also formed on the masks to produce a second pair of conjugated interference patterns that are inverted the first. Misalignment of the dark and light regions of the first interference patterns and the second interference patterns in both pairs of conjugated interference patterns is determined when patterns formed using the masks are overlaid. A magnification factor (of the interference pattern misalignment to the target misalignment) is calculated as a ratio of the difference of misalignment of the relatively dark and relatively light regions in the pairs of interference patterns, over twice the bias distance. The interference pattern misalignment is divided by the magnification factor to produce a self-referenced and self-calibrated target misalignment amount, which is then output.Type: GrantFiled: January 12, 2018Date of Patent: July 7, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Dongyue Yang, Xintuo Dai, Dongsuk Park, Minghao Tang, Md Motasim Bellah, Pavan Kumar Chinthamanipeta Sripadarao, Cheuk Wun Wong
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Publication number: 20200201955Abstract: Disclosed are embodiments of a system, method and computer program product for wafer-level design including chip and frame design. The embodiments employ three-dimensional (3D) emulation to preliminarily verify in-kerf optical macros included in a frame design layout. Specifically, 3D images of a given in-kerf optical macro at different process steps are generated by a 3D emulator and a determination is made as to whether or not that macro will be formed as predicted. If not, the plan for the macro is altered using an iterative design process. Once the in-kerf optical macros within the frame design layout have been preliminarily verified, wafer-level design layout verification, including chip and frame design layout verification, is performed. Once the wafer-level design layout has been verified, wafer-level design layout validation, including chip and frame design layout validation, is performed. Optionally, an emulation library can store results of 3D emulation processes for future use.Type: ApplicationFiled: December 19, 2018Publication date: June 25, 2020Inventors: Hojin Kim, Dongyue Yang, Dong-Ick Lee, Yue Zhou, Jae Ho Joung, Gregory Costrini, El Mehdi Bazizi, Dongsuk Park
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Publication number: 20200152498Abstract: Embodiments of the disclosure provides an apparatus for aligning layers of an integrated circuit (IC), the apparatus including: an insulator layer positioned above a semiconductor substrate; a first diffraction grating within a first region of the insulator layer, the first diffraction grating including a first grating material within the first region of the insulator layer; and a second diffraction grating within a second region of the insulator layer, the second grating including a second grating material within the second region of the insulator layer, wherein the second grating material is different from the first grating material, and wherein an optical contrast between the first and second grating materials is greater than an optical contrast between the second grating material and the insulator layer.Type: ApplicationFiled: November 13, 2018Publication date: May 14, 2020Inventors: Dongyue Yang, Keith H. Tabakman, Guanchen He, Xintuo Dai, Xueli Hao
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Patent number: 10635007Abstract: Embodiments of the disclosure provides an apparatus for aligning layers of an integrated circuit (IC), the apparatus including: an insulator layer positioned above a semiconductor substrate; a first diffraction grating within a first region of the insulator layer, the first diffraction grating including a first grating material within the first region of the insulator layer; and a second diffraction grating within a second region of the insulator layer, the second grating including a second grating material within the second region of the insulator layer, wherein the second grating material is different from the first grating material, and wherein an optical contrast between the first and second grating materials is greater than an optical contrast between the second grating material and the insulator layer.Type: GrantFiled: November 13, 2018Date of Patent: April 28, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Dongyue Yang, Keith H. Tabakman, Guanchen He, Xintuo Dai, Xueli Hao
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Publication number: 20200051923Abstract: In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.Type: ApplicationFiled: October 16, 2019Publication date: February 13, 2020Applicant: GLOBALFOUNDRIES INC.Inventors: Cung D. Tran, Huaxiang Li, Bradley Morgenfeld, Xintuo Dai, Sanggil Bae, Rui Chen, Md Motasim Bellah, Dongyue Yang, Minghao Tang, Christian J. Ayala, Ravi Prakash Srivastava, Kripa Nidhan Chauhan, Pavan Kumar Chinthamanipeta Sripadarao
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Patent number: 10504851Abstract: In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.Type: GrantFiled: February 26, 2018Date of Patent: December 10, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Cung D. Tran, Huaxiang Li, Bradley Morgenfeld, Xintuo Dai, Sanggil Bae, Rui Chen, Md Motasim Bellah, Dongyue Yang, Minghao Tang, Christian J. Ayala, Ravi Prakash Srivastava, Kripa Nidhan Chauhan, Pavan Kumar Chinthamanipeta Sripadarao
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Publication number: 20190363053Abstract: One illustrative example of an overlay mark disclosed herein includes four quadrants (I-IV). Each quadrant of the mark contains an inner periodic structure and an outer periodic structure. Each of the outer periodic structures includes a plurality of outer features. Each of the inner periodic structures includes a plurality of first inner groups, each of the first inner groups having a plurality of first inner features, each first inner group being oriented such that there is an end-to-end spacing relationship between each first inner group and a selected one of the outer features.Type: ApplicationFiled: May 22, 2018Publication date: November 28, 2019Inventors: Wei Zhao, Minghao Tang, Rui Chen, Dongyue Yang, Haiting Wang, Erik Geiss, Scott Beasor
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Publication number: 20190267329Abstract: In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.Type: ApplicationFiled: February 26, 2018Publication date: August 29, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Cung D. Tran, Huaxiang Li, Bradley Morgenfeld, Xintuo Dai, Sanggil Bae, Rui Chen, Md Motasim Bellah, Dongyue Yang, Minghao Tang, Christian J. Ayala, Ravi Prakash Srivastava, Kripa Nidhan Chauhan, Pavan Kumar Chinthamanipeta Sripadarao
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Publication number: 20190219930Abstract: Two pairs of alignment targets (one aligned, one misaligned by a bias distance) are formed on different masks to produce a first pair of conjugated interference patterns. Other pairs of alignment targets are also formed on the masks to produce a second pair of conjugated interference patterns that are inverted the first. Misalignment of the dark and light regions of the first interference patterns and the second interference patterns in both pairs of conjugated interference patterns is determined when patterns formed using the masks are overlaid. A magnification factor (of the interference pattern misalignment to the target misalignment) is calculated as a ratio of the difference of misalignment of the relatively dark and relatively light regions in the pairs of interference patterns, over twice the bias distance. The interference pattern misalignment is divided by the magnification factor to produce a self-referenced and self-calibrated target misalignment amount, which is then output.Type: ApplicationFiled: January 12, 2018Publication date: July 18, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Dongyue Yang, Xintuo Dai, Dongsuk Park, Minghao Tang, Md Motasim Bellah, Pavan Kumar Chinthamanipeta Sripadarao, Cheuk Wun Wong