Patents by Inventor Dongzhi Chi
Dongzhi Chi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230243030Abstract: A method for forming a transition metal dichalcogenide monolayer, which includes depositing a transition metal, a transition metal oxide, or a mixture thereof, on a substrate, introducing a chalcogen precursor to the transition metal, the transition metal oxide, or the mixture thereof, in the presence of an etching gas and a carrier gas at a first temperature, to form a transition metal dichalcogenide on the substrate from the transition metal, the transition metal oxide, or the mixture thereof, and subliming the transition metal dichalcogenide on the substrate in the presence of a pulsating supply of a vapor of the chalcogen precursor to form the transition metal dichalcogenide monolayer at a second temperature, wherein the vapor of the chalcogen precursor comprises a chalcogen vapor.Type: ApplicationFiled: June 28, 2021Publication date: August 3, 2023Inventors: Henry Medina Silva, Dongzhi Chi, Shi Wun Tong, Jianwei Chai, Shijie Wang
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Publication number: 20220278276Abstract: Herein provided is a multilayered structure including one or more nanocrystalline layers each comprising a transition metal dichalcogenide, one or more substantially amorphous electrically insulating layers each comprising a transition metal oxide, wherein the transition metal oxide comprises a transition metal which is identical to the transition metal of the transition metal dichalcogenide, wherein the one or more nanocrystalline layers and the one or more substantially amorphous electrically insulating layers are formed in an alternating manner, and wherein each of the one or more nanocrystalline layers is formed adjacent to the substantially amorphous insulating layer. A resistive memory device comprising the multilayered structure and a process of fabricating the multilayered structure are also disclosed herein.Type: ApplicationFiled: September 18, 2020Publication date: September 1, 2022Inventors: Henry MEDINA SILVA, Dongzhi CHI, Jianwei CHAI, Ming YANG, Shijie WANG, Shi Wun TONG, Carlos MANZANO
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Publication number: 20220178018Abstract: A method of forming a transition metal dichalcogenide layer on a substrate is provided. The method may include providing a transition metal oxide, a chalcogen source, a non-gaseous chalcogen scavenger, and a substrate, wherein the substrate is disposed downstream of the transition metal oxide and the chalcogen source, and wherein the non-gaseous chalcogen scavenger is disposed in proximity to the transition metal oxide; generating vapors of the transition metal oxide and vapors of the chalcogen source, wherein the non-gaseous chalcogen scavenger reacts preferentially with the vapors of the chalcogen source; disposing the vapors generated from the transition metal oxide and the chalcogen source on the substrate; and reacting the vapors of the transition metal oxide and the chalcogen source on the substrate to obtain the transition metal dichalcogenide layer on the substrate.Type: ApplicationFiled: March 11, 2020Publication date: June 9, 2022Inventors: Swee Liang Wong, Yee Fun Lim, Dongzhi Chi
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Patent number: 11257663Abstract: A sputtering system and a sputtering method are provided. The sputtering system includes a first electrode, a magnet and a second electrode. The first electrode is an elongated tube having a first end and a second end downstream of the first end. The first end is configured to receive a gas flow and the second end is placed next to a substrate. The magnet surrounds at least a portion of the elongated tube and is configured to generate a magnetic field in a space within the elongated tube. The second electrode is disposed within the elongated tube. A voltage is configured to be applied between the first and second electrodes to generate an electric field between the first and second electrodes.Type: GrantFiled: September 11, 2018Date of Patent: February 22, 2022Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCHInventors: Jianwei Chai, Shijie Wang, Dongzhi Chi, Ming Yang
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Publication number: 20210027924Abstract: The present disclosure generally relates to a soft magnetic composite (100) and a method (200) of manufacturing the soft magnetic composite (100). The soft magnetic composite (100) comprises composite elements (102) that are fused together. The composite elements (102) comprise: magnetic microparticles (104) formed of a soft magnetic material; and additive objects (106) deposited on the magnetic microparticles (104), the additive objects (106) being smaller than the magnetic microparticles (104), wherein the soft magnetic composite (100) is formed by an additive manufacturing process that fused the composite elements (102) together.Type: ApplicationFiled: March 22, 2019Publication date: January 28, 2021Inventors: Pei WANG, Cheng Cheh Dennis TAN, Dongzhi CHI
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Publication number: 20200279723Abstract: A sputtering system and a sputtering method are provided. The sputtering system includes a first electrode, a magnet and a second electrode. The first electrode is an elongated tube having a first end and a second end downstream of the first end. The first end is configured to receive a gas flow and the second end is placed next to a substrate. The magnet surrounds at least a portion of the elongated tube and is configured to generate a magnetic field in a space within the elongated tube. The second electrode is disposed within the elongated tube. A voltage is configured to be applied between the first and second electrodes to generate an electric field between the first and second electrodes.Type: ApplicationFiled: September 11, 2018Publication date: September 3, 2020Inventors: Jianwei Chai, Shijie Wang, Dongzhi Chi, Ming Yang
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Publication number: 20180105459Abstract: The present disclosure describes a multilayer coating, comprising at least one metal oxide layer; and a composite layer provided on said metal oxide layer, said composite layer comprising at least one metal layer disposed between at least two barrier layers, and wherein said barrier layers are substantially impermeable to oxygen. The multilayer coating may be useful as transparent heat reflectors on glass, plastic, and on low temperature processing transparent substrate for energy saving application.Type: ApplicationFiled: April 20, 2016Publication date: April 19, 2018Inventors: Goutam Kumar DALAPATI, Shijie WANG, Dongzhi CHI
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Patent number: 9802821Abstract: There is provided a method of preparing transition metal phosphide comprising the step of mixing a solution of a transition metal precursor and a phosphorous precursor under conditions to form the transition metal phosphide. There is also provided a transition metal phosphide particle made according to the method as defined herein. There is additionally provided a method of preparing a transition metal phosphide-based electrode used for producing hydrogen in the electrolysis of water.Type: GrantFiled: July 13, 2016Date of Patent: October 31, 2017Assignee: Agency for Science, Technology and ResearchInventors: Shuang-Yuan Zhang, Si Yin Tee, Ming-Yong Han, Kwok Wei Shah, Chin Sheng Chua, Dongzhi Chi, Andy Hor
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Publication number: 20170015558Abstract: There is provided a method of preparing transition metal phosphide comprising the step of mixing a solution of a transition metal precursor and a phosphorous precursor under conditions to form the transition metal phosphide. There is also provided a transition metal phosphide particle made according to the method as defined herein. There is additionally provided a method of preparing a transition metal phosphide-based electrode used for producing hydrogen in the electrolysis of water.Type: ApplicationFiled: July 13, 2016Publication date: January 19, 2017Inventors: Shuang-Yuan ZHANG, Si Yin TEE, Ming-Yong HAN, Kwok Wei SHAH, Chin Sheng CHUA, Dongzhi CHI, Andy HOR
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Publication number: 20090220782Abstract: A method of forming gallium arsenide (GaAs)-on-insulator includes providing a substrate and forming a diffusion barrier layer of a compound of formula AlxGa1-xAs on the substrate. A layer of GaAs is formed on the diffusion barrier layer of AlxGa1-xAs. The layer of AlxGa1-xAs is substantially completely oxidized to transform the layer of AlxGa1-xAs into an electrical insulator as well as a diffusion barrier.Type: ApplicationFiled: February 19, 2009Publication date: September 3, 2009Applicant: Agency for Science, Technology and ResearchInventors: Ching Kean CHIA, Dongzhi CHI, Jianrong DONG, Aaditya SRIDHARA
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Patent number: 7419905Abstract: A method of fabricating a gate electrode for a semiconductor comprising the steps of: providing a substrate; providing on the substrate a layer of a first material of thickness tp, the first material being selected from the group consisting of Si, Si1-x—Gex alloy, Ge and mixtures thereof and a layer of metal of thickness tm; and annealing the layers, such that substantially all of the first material and the metal are consumed during reaction with one another.Type: GrantFiled: January 29, 2004Date of Patent: September 2, 2008Assignee: Agency for Science, Technology and ResearchInventors: Dominique Mangelinck, Dongzhi Chi, Syamal Kumar Lahiri
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Patent number: 7335606Abstract: A NiSi layer over silicon that is thermally stable and can form even in the presence of oxides. The method of fabricating the nickel silicide layer includes providing a substrate comprising silicon, depositing a layer of at least a 3-component metal alloy comprising nickel on a surface of the substrate, and annealing the alloy and the substrate. The annealing temperature is less than 1000° C. The 3-component metal alloy can include Ni, Ti and Pt.Type: GrantFiled: March 15, 2004Date of Patent: February 26, 2008Assignee: Agency for Science, Technology and ResearchInventors: Dongzhi Chi, Tek Po Rinus, Soo Jin Chua
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Publication number: 20070272955Abstract: A nickel-based germanide contact includes a processing material that inhibits agglomeration of nickel-based germanide during processing to form the contact as well as during post-germanidation processes. The processing material is either in the form of a capping layer over the nickel layer or integrated into the nickel layer used to form the nickel-based contact. Reducing agglomeration improves electrical characteristics of the contact.Type: ApplicationFiled: July 27, 2004Publication date: November 29, 2007Applicant: Agency for science, Technology and ResearchInventors: Dongzhi Chi, Ka Lee, Tek Po Lee, Siao Liew, Hai Yao
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Publication number: 20060128125Abstract: A method of fabricating a gate electrode for a semiconductor comprising the steps of: providing a substrate; providing on the substrate a layer of a first material of thickness tp, the first material being selected from the group consisting of Si, Si1-x—Gex alloy, Ge and mixtures thereof and a layer of metal of thickness tm; and annealing the layers, such that substantially all of the first material and the metal are consumed during reaction with one another.Type: ApplicationFiled: January 29, 2004Publication date: June 15, 2006Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCHInventors: Dominique Mangelinck, Dongzhi Chi, Syamal Lahiri
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Publication number: 20050202673Abstract: A NiSi layer over silicon that is thermally stable and can form even in the presence of oxides. The method of fabricating the nickel silicide layer includes providing a substrate comprising silicon, depositing a layer of at least a 3-component metal alloy comprising nickel on a surface of the substrate, and annealing the alloy and the substrate. The annealing temperature is less than 1000° C. The 3-component metal alloy can include Ni, Ti and Pt.Type: ApplicationFiled: March 15, 2004Publication date: September 15, 2005Inventors: Dongzhi Chi, Tek Rinus, Soo Chua
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Patent number: 6531396Abstract: A method of fabricating a silicide layer on a silicon region of a semiconductor structure, the method comprising the steps of: providing a semiconductor structure having at least one silicon region on a surface thereof; depositing a layer comprising nickel and platinum on the at least one silicon layer; annealing the semiconductor structure and the nickel/platinum layer to react the nickel and the platinum with underlying silicon to form a nickel-platinum silicide, wherein annealing step takes place at temperature of between 680° C. and 720° C.Type: GrantFiled: November 17, 2000Date of Patent: March 11, 2003Assignee: Institute of Materials Research and EngineeringInventors: Dongzhi Chi, Syamal Kumar Lahiri, Dominique Mangelinck