Patents by Inventor Donhee Ham

Donhee Ham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11833346
    Abstract: The present invention generally relates to nanowires. In one aspect, the present invention is generally directed to systems and methods of individually addressing nanowires on a surface, e.g., that are substantially upstanding or vertically-oriented with respect to the surface. In some cases, one or more nanowires may be individually addressed using various integrated circuit (“IC”) technologies, such as CMOS. For example, the nanowires may form an array on top of an active CMOs integrated circuit.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: December 5, 2023
    Assignee: President and Fellows of Harvard College
    Inventors: Hongkun Park, Donhee Ham, Jeffrey T. Abbott, Ling Qin, Marsela Jorgolli, Tianyang Ye
  • Patent number: 11774396
    Abstract: Disclosed herein are an apparatus for electrically assessing and/or manipulating cells. One aspect is directed to electrically mapping cells on the surface of the semiconductor substrate via cross-electrode impedance measurements. Further according to some aspects, the electrode array allows for spatially addressable electrical stimulation and/or recording of electrical signals in real-time using the CMOS circuitry. Some of these aspects are directed to using an electrode array to perform cell patterning through electrochemical gas generation, and extracellular electrochemical mapping.
    Type: Grant
    Filed: September 8, 2022
    Date of Patent: October 3, 2023
    Assignee: President and Fellows of Harvard College
    Inventors: Hongkun Park, Jeffrey T. Abbott, Wenxuan Wu, Tianyang Ye, Han Sae Jung, Donhee Ham
  • Patent number: 11768196
    Abstract: Methods and systems for stimulating and monitoring electrogenic cells are described. Some systems for stimulating electrogenic cells are based on the injection of electric currents into the cells via electrodes connected to the cells. Such stimulators may comprise an impedance element having an input terminal and an output terminal coupled to an electrode, and a voltage follower coupled between the input terminal and the output terminal of the impedance element, the voltage follower being configured to maintain a substantially constant voltage between the input terminal and the output terminal of the impedance element. The impedance element may comprise one or more switched capacitors at least in some embodiments. In some embodiments, the voltage follower may be implemented using a source follower.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: September 26, 2023
    Assignee: President and Fellows of Harvard College
    Inventors: Donhee Ham, Jeffrey T. Abbott, Hongkun Park, Wenxuan Wu
  • Patent number: 11747321
    Abstract: Disclosed herein are an apparatus for electrically assessing and/or manipulating cells. One aspect is directed to electrically mapping cells on the surface of the semiconductor substrate via cross-electrode impedance measurements. Further according to some aspects, the electrode array allows for spatially addressable electrical stimulation and/or recording of electrical signals in real-time using the CMOS circuitry. Some of these aspects are directed to using an electrode array to perform cell patterning through electrochemical gas generation, and extracellular electrochemical mapping.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: September 5, 2023
    Assignee: President and Fellows of Harvard College
    Inventors: Donhee Ham, Jeffrey T. Abbott, Wenxuan Wu, Tianyang Ye, Han Sae Jung, Hongkun Park
  • Publication number: 20230189673
    Abstract: A nonvolatile memory device includes a resistance switching layer, a gate on the resistance switching layer, a gate oxide layer between the resistance switching layer and the gate, and a source and a drain, spaced apart from each other, on the resistance switching layer. A resistance value of the resistance switching layer is changed based on an illumination of light irradiated onto the resistance switching layer and is maintained as a changed resistance value.
    Type: Application
    Filed: February 10, 2023
    Publication date: June 15, 2023
    Applicants: Samsung Electronics Co., Ltd., President and Fellows Of Harvard College
    Inventors: Minhyun LEE, Houk JANG, Donhee HAM, Chengye LIU, Henry Julian HINTON, Haeryong KIM, Hyeonjin SHIN
  • Publication number: 20230184739
    Abstract: Disclosed herein are semiconductor devices to provide a CMOS-compatible, wafer-scale, multi-well platform that can be used for biomedical or other applications, and methods to operate the same. In some embodiments, circuitry is provided underneath a multiple-well array to electrically interface with electrodes in the wells. To interface with electrodes in a large array, circuitry may be fabricated on a single silicon (Si) wafer having a dimension that is at least the same or larger than that of the multiple-well array. According to one aspect of the present disclosure, standard CMOS fabrication process such as those known to be used in a standard semiconductor foundry may be used without expensive customization for complex fabrication procedures. This may help the production cost to be lowered in some cases.
    Type: Application
    Filed: August 19, 2022
    Publication date: June 15, 2023
    Applicant: President and Fellows of Harvard College
    Inventors: Donhee Ham, Wenxuan Wu, Jeffrey T. Abbott, Henry Julian Hinton, Hongkun Park
  • Patent number: 11600774
    Abstract: A nonvolatile memory device includes a resistance switching layer, a gate on the resistance switching layer, a gate oxide layer between the resistance switching layer and the gate, and a source and a drain, spaced apart from each other, on the resistance switching layer. A resistance value of the resistance switching layer is changed based on an illumination of light irradiated onto the resistance switching layer and is maintained as a changed resistance value.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: March 7, 2023
    Assignees: Samsung Electronics Co., Ltd., President and Fellows Of Harvard College
    Inventors: Minhyun Lee, Houk Jang, Donhee Ham, Chengye Liu, Henry Julian Hinton, Haeryong Kim, Hyeonjin Shin
  • Publication number: 20230056865
    Abstract: A method and apparatus with artificial network generation and/or implementation corresponding to a natural neural network are disclosed. The method includes performing an adjusting, based on a firing time difference between an action potential (AP) of a first biological neuron and a post-synaptic potential (PSP) of a second biological neuron, of a first conductance value of a first memory corresponding to the first and second biological neurons, adjusting the firing time difference based on the PSP of the second biological neuron, and performing another adjusting, by controlling another firing time difference between the AP of the first biological neuron and the PSP of the second biological neuron to be the adjusted firing time difference, of a second conductance value of the first memory corresponding to the first and second biological neurons.
    Type: Application
    Filed: July 21, 2022
    Publication date: February 23, 2023
    Applicants: SAMSUNG ELECTRONICS CO., LTD., President and Fellows of Harvard College
    Inventors: Seijoon Kim, Renjing Xu, Hongkun Park, Donhee Ham, SANG JOON KIM
  • Publication number: 20230014082
    Abstract: Disclosed herein are an apparatus for electrically assessing and/or manipulating cells. One aspect is directed to electrically mapping cells on the surface of the semiconductor substrate via cross-electrode impedance measurements. Further according to some aspects, the electrode array allows for spatially addressable electrical stimulation and/or recording of electrical signals in real-time using the CMOS circuitry. Some of these aspects are directed to using an electrode array to perform cell patterning through electrochemical gas generation, and extracellular electrochemical mapping.
    Type: Application
    Filed: September 8, 2022
    Publication date: January 19, 2023
    Applicant: President and Fellows of Harvard College
    Inventors: Hongkun Park, Jeffrey T. Abbott, Wenxuan Wu, Tianyang Ye, Han Sae Jung, Donhee Ham
  • Publication number: 20220397512
    Abstract: Disclosed herein are an apparatus for electrically assessing and/or manipulating cells. One aspect is directed to electrically mapping cells on the surface of the semiconductor substrate via cross-electrode impedance measurements. Further according to some aspects, the electrode array allows for spatially addressable electrical stimulation and/or recording of electrical signals in real-time using the CMOS circuitry. Some of these aspects are directed to using an electrode array to perform cell patterning through electrochemical gas generation, and extracellular electrochemical mapping.
    Type: Application
    Filed: July 29, 2022
    Publication date: December 15, 2022
    Applicant: President and Fellows of Harvard College
    Inventors: Donhee Ham, Jeffrey T. Abbott, Wenxuan Wu, Tianyang Ye, Han Sae Jung, Hongkun Park
  • Publication number: 20220320425
    Abstract: Provided are memristors and neuromorphic devices including the memristors. A memristor includes a lower electrode and an upper electrode that are apart from each other and first and second two-dimensional material layers that are arranged between the lower electrode and the upper electrode and stacked without a chemical bond therebetween.
    Type: Application
    Filed: June 9, 2022
    Publication date: October 6, 2022
    Applicants: Samsung Electronics Co., Ltd., President and Fellows Of Harvard College
    Inventors: Minhyun LEE, Dovran AMANOV, Renjing XU, Houk JANG, Haeryong KIM, Hyeonjin SHIN, Yeonchoo CHO, Donhee HAM
  • Patent number: 11374171
    Abstract: Provided are memristors and neuromorphic devices including the memristors. A memristor includes a lower electrode and an upper electrode that are apart from each other and first and second two-dimensional material layers that are arranged between the lower electrode and the upper electrode and stacked without a chemical bond therebetween.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: June 28, 2022
    Assignees: Samsung Electronics Co., Ltd., President and Fellows of Harvard College
    Inventors: Minhyun Lee, Dovran Amanov, Renjing Xu, Houk Jang, Haeryong Kim, Hyeonjin Shin, Yeonchoo Cho, Donhee Ham
  • Publication number: 20220147799
    Abstract: Disclosed is a neural computer including an image sensor capable of controlling a photocurrent. The neural computer according to an embodiment includes a preprocessor configured to receive an image and generate a feature map for the received image; a flattening unit configured to transform the feature map generated by the preprocessor into tabular data to provide data output; and an image classifier configured to classify images received through the preprocessor by using the data output by the flattening unit as an input value. The preprocessor includes an optical signal processor configured to receive the image and generate the feature map.
    Type: Application
    Filed: October 13, 2021
    Publication date: May 12, 2022
    Applicants: Samsung Electronics Co., Ltd., President and Fellows Of Harvard College
    Inventors: Changhyun KIM, Houk JANG, Henry Julian HINTON, Hyeonjin SHIN, Minhyun LEE, Donhee HAM
  • Publication number: 20220147805
    Abstract: Disclosed is an apparatus and method mapping a natural neural network into an electronic neural network device of an electronic device. The method includes constructing a neural network map of a natural neural network based on membrane potentials of a plurality of biological neurons of the natural neural network, where the membrane potentials correspond to at least two different respective forms of membrane potentials, and mapping the neural network map to the electronic neural network device. The constructing of the neural network map and the mapping of the neural network map implement learning of the electronic neural network device. The method may further includes obtaining an input or stimuli, activating the learned electronic neural network device, provided the obtained input or stimuli, to perform neural network operations, and generating a neural network result for the obtained input or stimuli based on a result of the activated learned electronic neural device.
    Type: Application
    Filed: November 11, 2021
    Publication date: May 12, 2022
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Donhee HAM, Sang Joon KIM
  • Publication number: 20210371846
    Abstract: Methods and systems for stimulating and monitoring electrogenic cells are described. Some systems for stimulating electrogenic cells are based on the injection of electric currents into the cells via electrodes connected to the cells. Such stimulators may comprise an impedance element having an input terminal and an output terminal coupled to an electrode, and a voltage follower coupled between the input terminal and the output terminal of the impedance element, the voltage follower being configured to maintain a substantially constant voltage between the input terminal and the output terminal of the impedance element. The impedance element may comprise one or more switched capacitors at least in some embodiments. In some embodiments, the voltage follower may be implemented using a source follower.
    Type: Application
    Filed: July 6, 2018
    Publication date: December 2, 2021
    Applicant: PRESIDENT AND FELLOWS OF HARVARD COLLEGE
    Inventors: Donhee Ham, Jeffrey T ABBOTT, Hongkun PARK, Wenxuan WU
  • Publication number: 20210187280
    Abstract: The present invention generally relates to nanowires. In one aspect, the present invention is generally directed to systems and methods of individually addressing nanowires on a surface, e.g., that are substantially upstanding or vertically-oriented with respect to the surface. In some cases, one or more nanowires may be individually addressed using various integrated circuit (“IC”) technologies, such as CMOS. For example, the nanowires may form an array on top of an active CMOs integrated circuit.
    Type: Application
    Filed: January 8, 2021
    Publication date: June 24, 2021
    Applicant: President and Fellows of Harvard College
    Inventors: Hongkun Park, Donhee Ham, Jeffrey T. Abbott, Ling Qin, Marsela Jorgolli, Tianyang Ye
  • Publication number: 20210151678
    Abstract: A nonvolatile memory device includes a resistance switching layer, a gate on the resistance switching layer, a gate oxide layer between the resistance switching layer and the gate, and a source and a drain, spaced apart from each other, on the resistance switching layer. A resistance value of the resistance switching layer is changed based on an illumination of light irradiated onto the resistance switching layer and is maintained as a changed resistance value.
    Type: Application
    Filed: November 10, 2020
    Publication date: May 20, 2021
    Applicants: Samsung Electronics Co., Ltd., President and Fellows Of Harvard College
    Inventors: Minhyun LEE, Houk JANG, Donhee HAM, Chengye LIU, Henry HINTON, Haeryong KIM, Hyeonjin SHIN
  • Patent number: 10910794
    Abstract: A light-emitting device includes a substrate including a photonic cavity and configured to function as a gate, an active layer including a two-dimensional material, a first conductive contact, and a second conductive contact. The wavelength range of light generated by the light-emitting device may be narrowed based on the photonic cavity being included in the substrate, and the intensity and wavelength range of the generated light may be controlled based on the substrate functioning as a gate.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: February 2, 2021
    Assignees: Samsung Electronics Co., Ltd., President and Fellows of Harvard College
    Inventors: Jinseong Heo, Minhyun Lee, Seongjun Park, Philip Kim, Hongkun Park, Donhee Ham
  • Publication number: 20200395540
    Abstract: Provided are memristors and neuromorphic devices including the memristors. A memristor includes a lower electrode and an upper electrode that are apart from each other and first and second two-dimensional material layers that are arranged between the lower electrode and the upper electrode and stacked without a chemical bond therebetween.
    Type: Application
    Filed: March 19, 2020
    Publication date: December 17, 2020
    Applicants: Samsung Electronics Co., Ltd., President and Fellows Of Harvard College
    Inventors: Minhyun LEE, Dovran AMANOV, Renjing XU, Houk JANG, Haeryong KIM, Hyeonjin SHIN, Yeonchoo CHO, Donhee HAM
  • Publication number: 20200292482
    Abstract: Methods and systems for monitoring the activity of electrogenic networks are described. One representative system includes an array of electrode coupled to an analyzer having a stimulator and a receiver. The electrode is placed in contact with an electrogenic cell. The electrodes can be shaped as nanowires, tubes, cavities and/or cones. The analyzer may be configured to operate in a voltage stimulation mode, in which the cells are stimulated via voltages and monitored via current, or in a current stimulation mode, in which the cells are stimulated via currents and monitored via voltages. The analyzers may be arranged as single-stage amplifiers, and may include a feedback loop shared between the stimulation signal path and the sensing signal path. The feedback loop may be arranged to provide overlapping stimulation and sensing of the electrogenic network's cells.
    Type: Application
    Filed: October 30, 2018
    Publication date: September 17, 2020
    Applicant: President and Fellows of Harvard College
    Inventors: Donhee Ham, Hongkun Park, Keith Krenek, Tianyang Ye, Jeffrey T. Abbott, Wenxuan Wu