Abstract: A method for fabricating an ultra-small pore or contact for use in chalcogenide memory cells specifically and in semiconductor devices generally in which disposable spacers are utilized to fabricate ultra-small pores or contacts. The pores thus defined have minimum lateral dimensions ranging from approximately 500 to 4000 Angstroms. The pores thus defined may then be used to fabricate a chalcogenide memory cell or other semiconductor devices.

Abstract: A method for fabricating an ultra-small pore or contact for use in chalcogenide memory cells specifically and in semiconductor devices generally in which disposable spacers are utilized to fabricate ultra-small pores or contacts. The pores thus defined have minimum lateral dimensions ranging from approximately 500 to 4000 Angstroms. The pores thus defined may then be used to fabricate a chalcogenide memory cell or other semiconductor devices.

Abstract: The present invention introduces the use of "local" etch stop layers having highly selective etch characteristics vis-a-vis insulating layers into which the contact/vias are etched. Any kind of conducting material which possesses etch selectivity to an insulator such as oxide (i.e. doped polysilicon, tungsten, tungsten silicide, titanium, titanium silicide, titanium nitride and the like) may be used and the process flow described herein uses conductively doped polysilicon as an example to accomplish this task without the need to add any extra photo or mask step to a conventional dynamic random access memory (DRAM) process flow and with the addition of a minimal number of deposition and etch steps. During a first masking step to open a contact, a subsequent etch opens up the P-channel gate area to thin down the underlying oxide. Polysilicon is then deposited which is followed by formation of an oxide.