Patents by Inventor Do-nyun Kim

Do-nyun Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260202759
    Abstract: An aerial image prediction apparatus for predicting an aerial image in a semiconductor lithography process according to an embodiment includes a memory in which an aerial image prediction program is stored and a processor configured to execute the program stored in the memory. The aerial image prediction program inputs positional information of a region of interest on a photomask into a physics-informed neural network-based learning model to predict an aerial image representing a light intensity distribution irradiated onto a photoresist layer after passing through the region of interest.
    Type: Application
    Filed: January 2, 2026
    Publication date: July 16, 2026
    Inventors: Do-Nyun KIM, Jinho LEE, Seoungwoo LEE
  • Publication number: 20260054467
    Abstract: Disclosed are a meta-sheet capable of independent design of a Poisson's ratio and a coefficient of thermal expansion, and a method of designing the same, the meta-sheet including: unit structures shaped like polygons, formed of beams, and arranged continuously with polygonal edges connected by hinges so that the meta-sheet can expand or contract at a predetermined Poisson's ratio as the unit structures are rotated by external force, wherein the beam is formed as a bilayer beam into which two materials different in the coefficient of thermal expansion are jointed in a longitudinal direction, and bending deformation occurs due to heat so that the meta-sheet can expand or contract by external heat.
    Type: Application
    Filed: February 21, 2025
    Publication date: February 26, 2026
    Inventors: Do-Nyun Kim, Duhwan Kang
  • Publication number: 20250356550
    Abstract: A method includes extracting first feature data by applying a backbone network of a machine learning model to a layout image representing a design for a target pattern, applying a hotspot segmentation network of the machine learning model to the first feature data, the hotspot segmentation network configured to generate a hotspot map representing a hotspot area of the layout image corresponding to a fault, obtaining, from the hotspot segmentation network, second feature data, and generating a scanning electron microscope (SEM) image of a wafer by applying an SEM image generation network of the machine learning model to the first feature data and the second feature data.
    Type: Application
    Filed: February 6, 2025
    Publication date: November 20, 2025
    Applicants: SAMSUNG ELECTRONICS CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Jaehoon KIM, Do-Nyun KIM, Jaekyung LIM, YunHyoung NAM
  • Publication number: 20250341786
    Abstract: A contour extraction model learning device for detecting a contour of a semiconductor lithography pattern includes a memory storing a contour extraction training program, and a processor configured to execute the contour extraction training program stored in the memory, wherein the contour extraction training program extracts a first contour image by inputting a SEM image of a new pattern to a contour extraction unit, generates a virtual SEM image by inputting the first contour image to a style transfer model, and trains the contour extraction model based on a training dataset in which the first contour image is matched with the virtual SEM image.
    Type: Application
    Filed: May 27, 2025
    Publication date: November 6, 2025
    Inventors: Do-Nyun KIM, Tae-Yeon KIM
  • Patent number: 12254621
    Abstract: Disclosed is an operating method of an electronic device for manufacture of a semiconductor device. The method includes receiving, at the electronic device, a computer-aided design (CAD) image for a lithography process of the semiconductor device, and generating, at the electronic device, a first scanning electron microscope (SEM) image and a first segment (SEG) image from the CAD image by using a machine learning-based module, and the first SEG image includes information about a location of a defect.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: March 18, 2025
    Assignees: Samsung Electronics Co., Ltd., Seoul National University R&DB Foundation
    Inventors: Do-Nyun Kim, Min-Cheol Kang, Kihyun Kim, Jaehoon Kim, Jaekyung Lim
  • Publication number: 20250046056
    Abstract: A conversion model construction device updates a generation module to process a first training image of a first type into a conversion image by using a separation outline module, updates the generation module to process the conversion image into a shape of a second training image of a second type by using a shape inference module, and trains the conversion model by updating the generation module such that the conversion image is determined as a real image by a discriminator module. The separation outline module separates a polygon of an input image from a background and distinguishes an outline, the shape inference module compares a border shape of a polygon included in the first image with a border shape of a polygon included in the second image and the discriminator module determines whether the input image is a real image or a fake image according to the set condition.
    Type: Application
    Filed: October 18, 2024
    Publication date: February 6, 2025
    Inventors: Do-Nyun KIM, Yun Hyoung NAM, Tae-Yeon KIM, Jae Hoon KIM
  • Patent number: 12118708
    Abstract: Disclosed is a wafer defect inference system, which includes a test equipment that receives a first image obtained by imaging circuit patterns formed on a semiconductor wafer by using a scanning electron microscope and a second image obtained by imaging a layout image of a mask for implementing the circuit pattern on the semiconductor wafer and combines the first image and the second image to generate a combination image, and at least one computing device that is capable of communicating with the test equipment and infers a defect associated with the circuit pattern formed on the semiconductor wafer. The computing device receives the combination image, performs machine learning for inferring the defect based on the combination image, and generates an output image including information about the defect based on the machine learning.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: October 15, 2024
    Assignees: Samsung Electronics Co., Ltd., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Min-Cheol Kang, Do-Nyun Kim, Jaehoon Kim, Woojoo Sim
  • Publication number: 20230069493
    Abstract: Disclosed is an operating method of an electronic device for manufacture of a semiconductor device. The method includes receiving, at the electronic device, a computer-aided design (CAD) image for a lithography process of the semiconductor device, and generating, at the electronic device, a first scanning electron microscope (SEM) image and a first segment (SEG) image from the CAD image by using a machine learning-based module, and the first SEG image includes information about a location of a defect.
    Type: Application
    Filed: July 1, 2022
    Publication date: March 2, 2023
    Applicants: Samsung Electronics Co., Ltd., Seoul National University, R&DB Foundation
    Inventors: Do-Nyun KIM, Min-Cheol KANG, Kihyun KIM, Jaehoon KIM, Jaekyung LIM
  • Publication number: 20220108436
    Abstract: Disclosed is a wafer defect inference system, which includes a test equipment that receives a first image obtained by imaging circuit patterns formed on a semiconductor wafer by using a scanning electron microscope and a second image obtained by imaging a layout image of a mask for implementing the circuit pattern on the semiconductor wafer and combines the first image and the second image to generate a combination image, and at least one computing device that is capable of communicating with the test equipment and infers a defect associated with the circuit pattern formed on the semiconductor wafer. The computing device receives the combination image, performs machine learning for inferring the defect based on the combination image, and generates an output image including information about the defect based on the machine learning.
    Type: Application
    Filed: September 2, 2021
    Publication date: April 7, 2022
    Applicants: Samsung Electronics Co., Ltd., Seoul National University, R&DB Foundation
    Inventors: Min-Cheol KANG, Do-Nyun KIM, Jaehoon KIM, Woojoo SIM
  • Patent number: 10289799
    Abstract: Techniques for controlling nucleic acid structures include determining, for each junction type, values for parameters indicating ground-state geometry and both translational and rotational stiffness coefficients. Topological design data indicates a number of bases in each helix connected to corresponding junctions. Initial positions of each base are determined by connecting helices to junctions using the ground-state geometry and arbitrary coordinates not confined to lattice coordinates. Misalignment vectors each indicate a difference in coordinates and orientations between initial positions of a pair of bases that are not adjacent in the initial positions but are adjacent or coincident in the design data. Forces and moments at the junctions to reduce misalignment magnitudes are determined based on the translational and rotational stiffness coefficients at each junction.
    Type: Grant
    Filed: October 3, 2015
    Date of Patent: May 14, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Mark Bathe, Keyao Pan, Do-Nyun Kim
  • Publication number: 20160103951
    Abstract: Techniques for controlling nucleic acid structures include determining, for each junction type, values for parameters indicating ground-state geometry and both translational and rotational stiffness coefficients. Topological design data indicates a number of bases in each helix connected to corresponding junctions. Initial positions of each base are determined by connecting helices to junctions using the ground-state geometry and arbitrary coordinates not confined to lattice coordinates. Misalignment vectors each indicate a difference in coordinates and orientations between initial positions of a pair of bases that are not adjacent in the initial positions but are adjacent or coincident in the design data. Forces and moments at the junctions to reduce misalignment magnitudes are determined based on the translational and rotational stiffness coefficients at each junction.
    Type: Application
    Filed: October 3, 2015
    Publication date: April 14, 2016
    Applicant: Massachusetts Institute of Technology
    Inventors: Mark Bathe, Keyao Pan, Do-Nyun Kim
  • Patent number: 8554489
    Abstract: Techniques for controlling properties of nucleic acid nanostructures include receiving data that indicates a sequence of nucleotides on at least a first strand of a nucleic acid. Values are determined for at least one physical property for each portion of the at least first strand. Based at least in part on a numerical model and the physical properties for each portion, a value is determined of at least one derived property of a nanostructure that comprises the at least first strand of nucleic acid. In some embodiments, information gained from the numerical model is used iteratively in order to optimize or improve one or more of the properties of the target DNA origami structure.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: October 8, 2013
    Assignee: Massachusetts Institute of Technology
    Inventors: Mark Bathe, Do-Nyun Kim, Hendrik Dietz
  • Publication number: 20120166152
    Abstract: Techniques for controlling properties of nucleic acid nanostructures include receiving data that indicates a sequence of nucleotides on at least a first strand of a nucleic acid. Values are determined for at least one physical property for each portion of the at least first strand. Based at least in part on a numerical model and the physical properties for each portion, a value is determined of at least one derived property of a nanostructure that comprises the at least first strand of nucleic acid. In some embodiments, information gained from the numerical model is used iteratively in order to optimize or improve one or more of the properties of the target DNA origami structure.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Inventors: Mark Bathe, Do-Nyun Kim, Hendrik Dietz
  • Patent number: 7861220
    Abstract: There is provided a method for generating an adaptive usage environment descriptor that considers a usage environment of a digital item. In a description of multimedia contents based on usage environment descriptor and user preference descriptor of the multimedia contents, a “PrecedencePreference” is defined in respective usage environment descriptor of the digital item, or an “AlternativePreference” is defined in descriptors of the digital item, or the “AlternativePreference” and the “PrecedencePreference” are simultaneously defined in a description of an adaptation condition to adaptively modify and describe the digital item.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: December 28, 2010
    Assignee: LG Electronics Inc.
    Inventors: Do-Nyun Kim, Yong-Hyun Park, Young-Won Song
  • Patent number: 7629754
    Abstract: A deflection yoke for a cathode ray tube improves assembly and productivity and enables effective control of magnetic field corrections during device processing. The deflection yoke includes a horizontal deflection coil located next to the outer circumference of a funnel to generate a horizontal magnetic field, and a vertical deflection coil installed at the outer circumference of the funnel to generate a vertical deflection magnetic field. The vertical deflection coil is insulated from the horizontal deflection coil. A ferrite core is located close to the vertical deflection coil to reduce the loss in the magnetic force generated from the horizontal and vertical deflection coils, and to enhance their magnetic efficiency. A correction unit is spaced apart from the horizontal deflection coil by a predetermined distance to correct a geometric distortion of the vertical and the horizontal deflection magnetic fields that is generated due to the vertical and horizontal deflection coils.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: December 8, 2009
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Do-Nyun Kim, Ran-Ji Lee, Je-Wook Nam, Chang-Ryon Byon, Hoo-Deuk Kim, Moon-Jin Kim, Sang-Hoon Lee
  • Publication number: 20060181229
    Abstract: A deflection yoke for a cathode ray tube improves assembly and productivity and enables effective control of magnetic field corrections during device processing. The deflection yoke includes a horizontal deflection coil located next to the outer circumference of a funnel to generate a horizontal magnetic field, and a vertical deflection coil installed at the outer circumference of the funnel to generate a vertical deflection magnetic field. The vertical deflection coil is insulated from the horizontal deflection coil. A ferrite core is located close to the vertical deflection coil to reduce the loss in the magnetic force generated from the horizontal and vertical deflection coils, and to enhance their magnetic efficiency. A correction unit is spaced apart from the horizontal deflection coil by a predetermined distance to correct a geometric distortion of the vertical and the horizontal deflection magnetic fields that is generated due to the vertical and horizontal deflection coils.
    Type: Application
    Filed: February 6, 2006
    Publication date: August 17, 2006
    Inventors: Do-Nyun Kim, Ran-Ji Lee, Je-Wook Nam, Chang-Ryon Byon, Hoo-Deuk Kim, Moon-Jin Kim, Sang-Hoon Lee
  • Patent number: 6794808
    Abstract: A funnel for a cathode ray tube includes a body portion having an opened end connected to a panel and an alignment mark formed on an outer surface of the body portion in the vicinity of the opened end, a neck portion for housing an electron gun, a yoke portion around which a deflection yoke is mounted, the yoke portion having a first end connected to the body portion at a top-of-round (TOR) and a second end connected to the neck portion. A convex portion having a thickness greater than 1 mm is provided on an outer portion of the body portion and/or yoke portion from the vicinity of the end of the alignment mark to the vicinity of the TOR in a direction of a tube axis.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: September 21, 2004
    Assignees: Samsung SDI Co., Ltd., Samsung Corning Co., Ltd.
    Inventors: Jun-Kyo In, Do-Nyun Kim, Jung-Mook Kim
  • Patent number: 6720727
    Abstract: A cathode ray tube for reducing a deflection power without any BSN problem is disclosed. The cathode ray tube has a panel, a funnel having a deflection yoke on an outer periphery thereof, and a neck connected to the cone of the funnel. A phosphor screen is arranged on an inner surface of the panel. The funnel includes a body connected to the panel, and a cone connected to the body. The cone has a deflection power reducing shape which is formed to have a range of length 0.25×L from an end of the cone at the neck where L is an entire length of the cone measured along an axis of symmetry of the cathode ray tube.
    Type: Grant
    Filed: June 21, 2000
    Date of Patent: April 13, 2004
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Bong-Woo Lee, Do-Nyun Kim
  • Publication number: 20030208375
    Abstract: There is provided a method for generating an adaptive usage environment descriptor that considers a usage environment of a digital item. In a description of multimedia contents based on usage environment descriptor and user preference descriptor of the multimedia contents, a “PrecedencePreference” is defined in respective usage environment descriptor of the digital item, or an “AlternativePreference” is defined in descriptors of the digital item, or the “AlternativePreference” and the “PrecedencePreference” are simultaneously defined in a description of an adaptation condition to adaptively modify and describe the digital item.
    Type: Application
    Filed: May 5, 2003
    Publication date: November 6, 2003
    Applicant: LG Electronics Inc.
    Inventors: Do-Nyun Kim, Yong-Hyun Park, Young-Won Song
  • Patent number: 6538369
    Abstract: A cathode ray tube with a central axis includes a panel with an inner phosphor screen, and a funnel connected to the panel. The funnel has a cone portion with a neck sealing side, and a body portion extended from he cone portion to the panel. A deflection yoke is externally mounted around the funnel. A neck is connected to the neck sealing side of the cone portion. An electron gun is mounted within the neck. The funnel is structured to satisfy the following condition: 0.52+0.001×(&agr;/2+&phgr;)<b/a<0.74+0.001×(&agr;/2+&phgr;) where a indicates the distance (mm) between the reference line R/L and the too of round TOR on the tube axis line, b indicates the disance (mm) between the reference line and the neck sealing side of the cone portion on the tube axis Z line, &agr; indicates the deflection angle (degree), and &phgr; indicates the diameter (mm) of the neck.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: March 25, 2003
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Bong-Woo Lee, Do-Nyun Kim