Patents by Inventor Doo Bock LEE
Doo Bock LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11483505Abstract: In accordance with an embodiment of the present disclosure, an image synchronization device includes a light emitting source configured to emit light at intervals of a predetermined time, a sampling phase calibration circuit configured to calibrate a sampling phase of each of the first image sensor and the second image sensor on the basis of a light emitting timing of the light emitting source and a delay calibration circuit configured to generate delay information on the basis of a result of comparison between first image information transmitted from the first image sensor and second image information transmitted from the second image sensor.Type: GrantFiled: June 14, 2018Date of Patent: October 25, 2022Assignee: SK hynix Inc.Inventors: Chang Hyun Kim, Wan Jun Roh, Doo Bock Lee, Seung Hun Lee, Jae Jin Lee, Chun Seok Jeong
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Patent number: 11380676Abstract: A semiconductor system includes a control device, and a semiconductor apparatus coupled with the control device through a first line and a second line. A loading of the second line is greater than a loading of the first line, wherein the semiconductor apparatus includes a first receiving circuit which is electrically coupled with the first line and a second receiving circuit which is electrically coupled with the second line. Further a loading between the first line and the first receiving circuit is greater than a loading between the second line and the second receiving circuit.Type: GrantFiled: December 1, 2020Date of Patent: July 5, 2022Assignee: SK hynix Inc.Inventors: Joong-Ho Kim, Hyun Woo Kwack, Ki Jong Lee, Doo Bock Lee
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Publication number: 20210377483Abstract: In accordance with an embodiment of the present disclosure, an image synchronization device includes a light emitting source configured to emit light at intervals of a predetermined time, a sampling phase calibration circuit configured to calibrate a sampling phase of each of the first image sensor and the second image sensor on the basis of a light emitting timing of the light emitting source and a delay calibration circuit configured to generate delay information on the basis of a result of comparison between first image information transmitted from the first image sensor and second image information transmitted from the second image sensor.Type: ApplicationFiled: June 14, 2018Publication date: December 2, 2021Inventors: Chang Hyun KIM, Wan Jun ROH, Doo Bock LEE, Seung Hun LEE, Jae Jin LEE, Chun Seok JEONG
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Publication number: 20210241814Abstract: A data receiving device includes a clock receiver and a plurality of data receivers. The clock receiver is configured to generate a plurality of internal clock signals from a clock signal and a complementary clock signal based on a switching enable signal. The plurality of data receivers are configured to receive data and a reference voltage and compare the data with the reference voltage in synchronization with the plurality of internal clock signals, respectively, to generate first internal data. Among the plurality of data receivers, a data receiver receiving an internal clock signal, of which a logic level transitions signals when a logic level of the switching enable signal transitions, is configured to change a voltage level of the reference voltage when the logic level of the switching enable signal transitions.Type: ApplicationFiled: July 14, 2020Publication date: August 5, 2021Applicant: SK hynix Inc.Inventors: Doo Bock LEE, Yong Suk CHOI
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Patent number: 11062757Abstract: A data receiving device includes a clock receiver and a plurality of data receivers. The clock receiver is configured to generate a plurality of internal clock signals from a clock signal and a complementary clock signal based on a switching enable signal. The plurality of data receivers are configured to receive data and a reference voltage and compare the data with the reference voltage in synchronization with the plurality of internal clock signals, respectively, to generate first internal data. Among the plurality of data receivers, a data receiver receiving an internal clock signal, of which a logic level transitions signals when a logic level of the switching enable signal transitions, is configured to change a voltage level of the reference voltage when the logic level of the switching enable signal transitions.Type: GrantFiled: July 14, 2020Date of Patent: July 13, 2021Assignee: SK hynix Inc.Inventors: Doo Bock Lee, Yong Suk Choi
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Publication number: 20210082909Abstract: A semiconductor system includes a control device, and a semiconductor apparatus coupled with the control device through a first line and a second line. A loading of the second line is greater than a loading of the first line, wherein the semiconductor apparatus includes a first receiving circuit which is electrically coupled with the first line and a second receiving circuit which is electrically coupled with the second line. Further a loading between the first line and the first receiving circuit is greater than a loading between the second line and the second receiving circuit.Type: ApplicationFiled: December 1, 2020Publication date: March 18, 2021Applicant: SK hynix Inc.Inventors: Joong-Ho KIM, Hyun Woo KWACK, Ki Jong LEE, Doo Bock LEE
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Patent number: 10867992Abstract: A semiconductor system includes a control device, and a semiconductor apparatus coupled with the control device through a first line and a second line. A loading of the second line is greater than a loading of the first line, wherein the semiconductor apparatus includes a first receiving circuit which is electrically coupled with the first line and a second receiving circuit which is electrically coupled with the second line. Further a loading between the first line and the first receiving circuit is greater than a loading between the second line and the second receiving circuit.Type: GrantFiled: December 27, 2017Date of Patent: December 15, 2020Assignee: SK hynix Inc.Inventors: Joong-Ho Kim, Hyun Woo Kwack, Ki Jong Lee, Doo Bock Lee
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Patent number: 10847194Abstract: An input/output circuit includes a data buffer group configured to buffer data received through data lines, a data strobe buffer configured to buffer a data strobe signal to output a buffered data strobe clock, a digitally controlled delay line configured to output delay data by controlling skew of the buffered data according to a delay code, a data strobe clock output circuit configured to generate a delay data strobe clock in response to the buffered data strobe clock, a sampler configured to sample the delay data according to the delay data strobe clock to output sampled data, and a de-skew circuit configured to update the delay code according to the sampled data.Type: GrantFiled: November 19, 2018Date of Patent: November 24, 2020Assignee: SK hynix Inc.Inventors: Dong Hyun Kim, Dae Han Kwon, Kwan Su Shon, Soon Ku Kang, Jung Hyun Shin, Doo Bock Lee, Yo Han Jeong, Eun Ji Choi, Tae Jin Hwang
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Publication number: 20190287587Abstract: An input/output circuit includes a data buffer group configured to buffer data received through data lines, a data strobe buffer configured to buffer a data strobe signal to output a buffered data strobe clock, a digitally controlled delay line configured to output delay data by controlling skew of the buffered data according to a delay code, a data strobe clock output circuit configured to generate a delay data strobe clock in response to the buffered data strobe clock, a sampler configured to sample the delay data according to the delay data strobe clock to output sampled data, and a de-skew circuit configured to update the delay code according to the sampled data.Type: ApplicationFiled: November 19, 2018Publication date: September 19, 2019Inventors: Dong Hyun KIM, Dae Han KWON, Kwan Su SHON, Soon Ku KANG, Jung Hyun SHIN, Doo Bock LEE, Yo Han JEONG, Eun Ji CHOI, Tae Jin HWANG
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Publication number: 20180358355Abstract: A semiconductor system includes a control device, and a semiconductor apparatus coupled with the control device through a first line and a second line. A loading of the second line is greater than a loading of the first line, wherein the semiconductor apparatus includes a first receiving circuit which is electrically coupled with the first line and a second receiving circuit which is electrically coupled with the second line. Further a loading between the first line and the first receiving circuit is greater than a loading between the second line and the second receiving circuit.Type: ApplicationFiled: December 27, 2017Publication date: December 13, 2018Applicant: SK hynix Inc.Inventors: Joong-Ho KIM, Hyun Woo KWACK, Ki Jong LEE, Doo Bock LEE
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Patent number: 9813070Abstract: The present invention relates to a method for generating a reference signal to drive a display apparatus. A method according to the present invention may comprise generating a reference signal having a training pattern being repeated with a periodicity of two clock terms (CTs); and transmitting the reference signal to a phase locked loop (PLL). Each CT has a single embedded clock bit (CB) and a plurality of data bits, and the reference signal has a rising edge at a start point of a first CB corresponding to a first unit interval (UI) of a first CT, and a rising edge at an end point of a second CB corresponding to a first UI of a second CT. According to exemplary embodiments of the present disclosure, energy consumption and EMI effects can be remarkably reduced, and a complexity of PLL can be reduced.Type: GrantFiled: February 16, 2016Date of Patent: November 7, 2017Assignee: POSTECH ACADEMY—INDUSTRY FOUNDATIONInventors: Jae Joon Kim, Doo Bock Lee, Jun Ki Park, Eun Woo Song
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Publication number: 20160241251Abstract: The present invention relates to a method for generating a reference signal to drive a display apparatus. A method according to the present invention may comprise generating a reference signal having a training pattern being repeated with a periodicity of two clock terms (CTs); and transmitting the reference signal to a phase locked loop (PLL). Each CT has a single embedded clock bit (CB) and a plurality of data bits, and the reference signal has a rising edge at a start point of a first CB corresponding to a first unit interval (UI) of a first CT, and a rising edge at an end point of a second CB corresponding to a first UI of a second CT. According to exemplary embodiments of the present disclosure, energy consumption and EMI effects can be remarkably reduced, and a complexity of PLL can be reduced.Type: ApplicationFiled: February 16, 2016Publication date: August 18, 2016Inventors: Jae Joon KIM, Doo Bock LEE, Jun Ki PARK, Eun Woo SONG