Abstract: In accordance with the present invention, there is provided a method for manufacturing a semiconductor package. The method comprises the initial step of applying first and second photoresist layers to respective ones of opposed first and second surfaces of a metal plate which includes a die paddle and a plurality of leads extending at least partially about the die paddle in spaced relation thereto. The first and second photoresist layers are then patterned to expose the die paddle and prescribed portions of each of the leads. Thereafter, first and second conductive layers are applied to portions of respective ones of the first and second surfaces which are not covered by the first and second photoresist layers. The first and second photoresist layers are then removed to facilitate the creation of an exposed area in each of leads which is not covered by the first and second conductive layers.

Abstract: In accordance with the present invention, there is provided a method for manufacturing a leadframe. The method comprises the initial step of bonding a primary leadframe to an adhesive tape layer, the primary leadframe including a die paddle and a plurality of leads which extend at least partially about the die paddle in spaced relation thereto. Thereafter, a photo resist is applied to the primary leadframe and to the adhesive tape layer. The photo resist is then patterned to define at least one exposed area in each of the leads of the primary leadframe. The exposed areas of the leads are then etched to divide the leads into an inner set which extends at least partially about the die paddle and an outer set which extends at least partially about the inner set. Thereafter, the photo resist is removed from the die paddle and from the inner and outer sets of the leads.

Abstract: A stackable semiconductor package is disclosed that includes a semiconductor die coupled to a metal leadframe. The semiconductor die is coupled to a die pad and is electrically coupled to leads of the leadframe. The semiconductor die, the die pad, and an inner lead portion of each of the leads is embedded in an encapsulant, and an outer lead portion of each of the leads is free of the encapsulant. A surface of the die pad and of the inner lead portion of each of the leads is exposed in a plane with an exterior first surface of the encapsulant. The outer lead portion is vertically such that a mounting surface of the outer lead portion is provided below an opposite second surface of the encapsulant. Other semiconductor packages or electronic devices may be stacked on and electrically coupled to the exposed surface of the inner lead portions.

Abstract: A package for an integrated circuit device, having a die, a die pad, leads, bond wire, and an encapsulant. The lower surfaces of the die pad and the leads are provided with stepped profiles. Structures extending from lateral sides of the leads are formed to prevent the leads from being pulled horizontally from the package. Encapsulant material fills beneath the recessed, substantially horizontal surfaces of the die pad and the leads, and thereby prevents the die pad and the leads from being pulled vertically from the package body. Other portions of the die pad and the leads are exposed within the package for connecting the package externally.

Abstract: Embodiments of a semiconductor package and manufacturing methods therefor are disclose. An exemplary package comprises an optical semiconductor chip having input and output pads on an upper surface thereof. A transparent plate is bonded to the chip via a dam located within the input and output pads. The chip is mounted within an aperture through a planar circuit board. Wires electrically connect the input and output pads to circuit patterns of the circuit board. An encapsulant fills the aperture, and supports the chip therein. Interconnects are formed on the lower surface of the circuit board. An alternative embodiment omits the dam and the wires and employs a flip chip style connection between the chip and circuit patterns on the transparent plate. The transparent is supported by and attached to the upper surface of the planar circuit board.