Abstract: A display device includes a substrate, a semiconductor layer disposed on the substrate, and including a first channel portion, a second channel portion, a connecting portion disposed between the first channel portion and the second channel portion, and electrode regions, a first insulating layer disposed on the semiconductor layer, a gate conductor disposed on the first insulating layer and including a first gate electrode overlapping the first channel portion and a second gate electrode overlapping the second channel portion, signal lines disposed on the substrate, a first electrode electrically connected to at least one of electrode regions of the semiconductor layer, an emission layer disposed on the first electrode, and a second electrode disposed on the emission layer, and the first channel portion and the second channel portion of the semiconductor layer each have a first width greater than a second width of the connecting portion.

Abstract: A memory device includes; a memory cell array including a memory cell connected to a bit line, a page buffer unit receiving data from the memory cell via the bit line, and a contact unit providing an electrical path through which the data is communicated from the memory cell array to the page buffer unit, wherein the contact unit comprises a sub-bit line configured to connect the bit line via a first contact with the page buffer unit via a second contact.

Abstract: A memory device includes; a memory cell array including a memory cell connected to a bit line, a page buffer unit receiving data from the memory cell via the bit line, and a contact unit providing an electrical path through which the data is communicated from the memory cell array to the page buffer unit, wherein the contact unit comprises a sub-bit line configured to connect the bit line via a first contact with the page buffer unit via a second contact.

Abstract: A memory device includes; a memory cell array including a memory cell connected to a bit line, a page buffer unit receiving data from the memory cell via the bit line, and a contact unit providing an electrical path through which the data is communicated from the memory cell array to the page buffer unit, wherein the contact unit comprises a sub-bit line configured to connect the bit line via a first contact with the page buffer unit via a second contact.

Abstract: A flash memory device includes: a memory cell array including pluralities of blocks; a block status storage unit including pluralities of latch cells arranged in rows and columns to store block status information signals corresponding to each of the blocks and providing the block status information signals in response to each of the write and read addresses; and a controller regulating an access to the memory cell array in response to the block status information signals. The block status storage unit provides information about whether a read address input during a read-while-write operation or suspend read operation is valid, and offers information about whether a current block is a write block or a write protection block.

Abstract: In a flash memory device, a multi-block erase operation is performed by applying stepwise increasing erase voltages to selected memory blocks during a first erase period and then applying fixed erase voltages to the selected memory blocks during a second erase period. Once a selected memory block is successfully erased in the first erase period, the device prevents erase voltages from being applied to the selected memory block for a remaining part of the first erase period.

Abstract: A method of post-programming a flash memory device includes the steps of: post-programming memory cells of a selected word line in a predetermined unit; determining, after incrementing an address for selecting the next word line, whether the incremented address matches one of reference addresses; and varying the post-programming unit of the selected memory cells whenever the incremented address matches one of reference addresses.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array of a plurality of memory cells; and a voltage generating circuit for generating a programming voltage to be applied to the memory cells. The voltage generating circuit includes a first voltage generating unit for generating a negative voltage through a first charge pump; and a second voltage generating unit for generating a positive voltage through a second charge pump. During an accelerated programming operation, the first voltage generating unit increases a pumping efficiency of the first charge pump using an external power supply voltage, and the second voltage generating unit directly outputs the external power supply voltage.

Abstract: A voltage generation circuit of a flash memory device includes a high voltage generator, a word line voltage generator, and a column selection voltage switch. The high voltage generator is configured to increase an internal power voltage from a first voltage to a second voltage which is higher than the first voltage. The word line voltage regulator is configured to generate an incremental step pulse based on the internal power voltage, where the incremental step pulse is output as a word line program voltage before the internal power voltage reaches the second voltage. The column selection voltage switch is configured to output a column selection voltage for selecting a bit line based on the internal power voltage.

Abstract: A flash memory device comprises an array of memory cells arranged in rows and columns and a word line voltage generating circuit adapted to generate a plurality of read voltages at the same time during a multi-bit read operation. The device further comprises a row selecting circuit adapted to select one of the rows and drive the selected row with a word line voltage, and voltage lines transmitting the respective read voltages to the row selecting circuit as the word line voltage. The read voltages are supplied to the respective voltage lines before starting read periods of the multi-bit read operation.

Abstract: A voltage generation circuit of a flash memory device includes a high voltage generator, a word line voltage generator, and a column selection voltage switch. The high voltage generator is configured to increase an internal power voltage from a first voltage to a second voltage which is higher than the first voltage. The word line voltage regulator is configured to generate an incremental step pulse based on the internal power voltage, where the incremental step pulse is output as a word line program voltage before the internal power voltage reaches the second voltage. The column selection voltage switch is configured to output a column selection voltage for selecting a bit line based on the internal power voltage.

Abstract: A flash memory device includes: a memory cell array including pluralities of blocks; a block status storage unit including pluralities of latch cells arranged in rows and columns to store block status information signals corresponding to each of the blocks and providing the block status information signals in response to each of the write and read addresses; and a controller regulating an access to the memory cell array in response to the block status information signals. The block status storage unit provides information about whether a read address input during a read-while-write operation or suspend read operation is valid, and offers information about whether a current block is a write block or a write protection block.

Abstract: A method of post-programming a flash memory device includes the steps of: post-programming memory cells of a selected word line in a predetermined unit; determining, after incrementing an address for selecting the next word line, whether the incremented address matches one of reference addresses; and varying the post-programming unit of the selected memory cells whenever the incremented address matches one of reference addresses.

Abstract: In a flash memory device, a multi-block erase operation is performed by applying stepwise increasing erase voltages to selected memory blocks during a first erase period and then applying fixed erase voltages to the selected memory blocks during a second erase period. Once a selected memory block is successfully erased in the first erase period, the device prevents erase voltages from being applied to the selected memory block for a remaining part of the first erase period.

Abstract: A NOR flash memory device configured to perform a program operation using an ISPP scheme, and comprising a plurality of memory cells, a word line voltage generator, and a scan controller is provided. A method of programming the NOR flash memory device comprising a bit scan method is also provided. The maximum number of cells that may be programmed simultaneously in the bit scan method is indicated by a scan bit number. The scan bit number may be changed by the scan controller during the program operation.

Abstract: A flash memory device includes a write driver for driving a data line according to data to be written in a flash memory cell during a program period, a sense amplifier circuit for sensing and amplifying the data stored in the flash memory cell during a program verify period, and an insulation circuit for electrically insulating the sense amplifier circuit from the data line during an operation period of the write driver.

Abstract: A flash memory device comprises an array of memory cells arranged in rows and columns and a word line voltage generating circuit adapted to generate a plurality of read voltages at the same time during a multi-bit read operation. The device further comprises a row selecting circuit adapted to select one of the rows and drive the selected row with a word line voltage, and voltage lines transmitting the respective read voltages to the row selecting circuit as the word line voltage. The read voltages are supplied to the respective voltage lines before starting read periods of the multi-bit read operation.

Abstract: A NOR flash memory device configured to perform a program operation using an ISPP scheme, and comprising a plurality of memory cells, a word line voltage generator, and a scan controller is provided. A method of programming the NOR flash memory device comprising a bit scan method is also provided. The maximum number of cells that may be programmed simultaneously in the bit scan method is indicated by a scan bit number. The scan bit number may be changed by the scan controller during the program operation.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array of a plurality of memory cells; and a voltage generating circuit for generating a programming voltage to be applied to the memory cells. The voltage generating circuit includes a first voltage generating unit for generating a negative voltage through a first charge pump; and a second voltage generating unit for generating a positive voltage through a second charge pump. During an accelerated programming operation, the first voltage generating unit increases a pumping efficiency of the first charge pump using an external power supply voltage, and the second voltage generating unit directly outputs the external power supply voltage.

Abstract: A flash memory device includes a write driver for driving a data line according to data to be written to a flash memory cell during a program period, a sense amplifier circuit for sensing and amplifying the data stored in the flash memory cell during a program verify period, and an isolation circuit for electrically isolating the sense amplifier circuit from the data line during an operation period of the write driver. Another embodiment includes a second isolation circuit adapted to isolating the write driver from the data line during the program verify period, reducing the load on the sense amplifier, and thus enhancing operating speed.