Abstract: According to an embodiment of the present invention, a substrate processing apparatus including: a chamber in which a process is performed on a substrate; a susceptor installed in the chamber to support the substrate; and a showerhead installed above the susceptor, and the showerhead includes: a plurality of inner injection holes defined in an inner area corresponding to a portion above the substrate and injecting a reaction gas downward; and a plurality of outer injection holes defined in an outer area corresponding to a portion outside the inner area and injecting an inert gas along an inner wall of the chamber.

Abstract: According to an embodiment of the present invention, a method for forming a thin film includes loading an object to be processed into a chamber, and while controlling the temperature of the object to be processed to be 400° C. or less, supplying an Si source gas and an oxidizing gas into the chamber to form a silicon oxide film on the surface of the object to be processed, wherein the oxidizing gas is heated to a temperature exceeding 400° C. before being supplied into the chamber.

Abstract: Provided is a method for forming an epitaxial layer at a low temperature. The method for forming the epitaxial layer includes transferring a substrate into an epitaxial chamber and performing an epitaxial process on the substrate to form an epitaxial layer on the substrate. The epitaxial process includes heating the substrate at a temperature of about 700° C. or less and injecting a silicon gas into the epitaxial chamber in a state in which the inside of the epitaxial chamber is adjusted to a pressure of about 300 Torr or less to form a first epitaxial layer, stopping the injection of the silicon gas and injecting a purge gas into the epitaxial chamber to perform first purge inside the epitaxial chamber, heating the substrate at a temperature of about 700° C.

Abstract: Provided is a method for forming an epitaxial layer at a low temperature. The method for forming the epitaxial layer includes transferring a substrate into an epitaxial chamber and performing an epitaxial process on the substrate to form an epitaxial layer on the substrate. The epitaxial process includes heating the substrate at a temperature of about 700° C. or less and injecting a silicon gas into the epitaxial chamber in a state in which the inside of the epitaxial chamber is adjusted to a pressure of about 300 Torr or less to form a first epitaxial layer, stopping the injection of the silicon gas and injecting a purge gas into the epitaxial chamber to perform first purge inside the epitaxial chamber, heating the substrate at a temperature of about 700° C.

Abstract: A non-volatile memory device includes a semiconductor substrate, a well region situated on the semiconductor substrate, a floating gate situated on the well region, a floating gate channel region, a control gate situated on both sides of the floating gate, a control gate channel region, and an ion implantation area for regulating a program threshold voltage integrally formed between an area underneath of the floating gate and the control gate and a foreside of the well region, wherein a doping concentration of the ion implantation area for regulating a program threshold voltage is greater than a doping concentration of the well region. Therefore, the non-volatile memory device of examples integrally forms an ion implantation area for regulating a program threshold voltage irrespective of a channel region of a floating gate and a control gate so as to guarantee durability of a non-volatile memory device.

Abstract: A non-volatile memory device includes a semiconductor substrate, a well region situated on the semiconductor substrate, a floating gate situated on the well region, a floating gate channel region, a control gate situated on both sides of the floating gate, a control gate channel region, and an ion implantation area for regulating a program threshold voltage integrally formed between an area underneath of the floating gate and the control gate and a foreside of the well region, wherein a doping concentration of the ion implantation area for regulating a program threshold voltage is greater than a doping concentration of the well region. Therefore, the non-volatile memory device of examples integrally forms an ion implantation area for regulating a program threshold voltage irrespective of a channel region of a floating gate and a control gate so as to guarantee durability of a non-volatile memory device.

Abstract: A nonvolatile memory device and a method of manufacturing thereof are provided. The method includes forming a floating gate on a substrate, forming a dielectric layer to conform to a shape of the floating gate, forming a conductive layer to form a control gate on the substrate, the control gate covering the floating gate and the dielectric layer, forming a photoresist pattern on one side of the conductive layer, forming the control gate in the form of a spacer to surround sides of the floating gate, the forming of the control gate including performing an etch-back on the conductive layer until a portion of the dielectric layer on the floating gate is exposed, and forming a poly pad, to which a plurality of contact plugs are connected, on one side of the control gate, the forming of the poly pad including removing the photoresist pattern.

Abstract: A nonvolatile memory device and a method of manufacturing thereof are provided. The method includes forming a floating gate on a substrate, forming a dielectric layer to conform to a shape of the floating gate, forming a conductive layer to form a control gate on the substrate, the control gate covering the floating gate and the dielectric layer, forming a photoresist pattern on one side of the conductive layer, forming the control gate in the form of a spacer to surround sides of the floating gate, the forming of the control gate including performing an etch-back on the conductive layer until a portion of the dielectric layer on the floating gate is exposed, and forming a poly pad, to which a plurality of contact plugs are connected, on one side of the control gate, the forming of the poly pad including removing the photoresist pattern.