Patents by Inventor Doo-Yeul Kim

Doo-Yeul Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device and associated data read method
    Patent number: 6738295
    Abstract: The inventive semiconductor memory device includes a data output buffer adapted to receive input data responsive to an on time control signal and adapted to buffer the input data responsive to a latch clock signal. A first clock signal generating means is adapted to generate a first clock signal responsive to a reference signal. A second clock signal generating means is adapted to generate a second clock signal responsive to the first clock signal and a mode signal. A latency signal generating means is adapted to generate a latency signal responsive to the mode signal. A latch clock generating means is adapted to generate the latch clock signal responsive to the second clock signal and the mode signal. And an on time control signal generating means is adapted to generate the on time control signal responsive to the second clock signal and the latency signal.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: May 18, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Doo-Yeul Kim
  • Semiconductor memory device and associated data read method
    Publication number: 20040022118
    Abstract: The inventive semiconductor memory device includes a data output buffer adapted to receive input data responsive to an on time control signal and adapted to buffer the input data responsive to a latch clock signal. A first clock signal generating means is adapted to generate a first clock signal responsive to a reference signal. A second clock signal generating means is adapted to generate a second clock signal responsive to the first clock signal and a mode signal. A latency signal generating means is adapted to generate a latency signal responsive to the mode signal. A latch clock generating means is adapted to generate the latch clock signal responsive to the second clock signal and the mode signal. And an on time control signal generating means is adapted to generate the on time control signal responsive to the second clock signal and the latency signal.
    Type: Application
    Filed: May 30, 2003
    Publication date: February 5, 2004
    Inventor: Doo-Yeul Kim