Abstract: A display device includes: first pixels in a first pixel region and connected to first scan lines; second pixels in a second pixel region that is located at a side of the first pixel region and has a width smaller than a width of the first pixel region, and connected to second scan lines; third pixels in a third pixel region that is spaced apart from the second pixel region and has a width smaller than the width of the first pixel region, and connected to third scan lines; a load matching unit in a peripheral region at an outside of the second pixel region and the third pixel region, and configured to match loads of the second scan lines and the third scan lines to that of the first scan lines; and a protection unit connected between the second and third pixels and the load matching unit.

Abstract: A display device includes first pixels in a first pixel area and coupled with first scan lines, first scan stage circuits in a first peripheral area outside the first pixel area, and configured to supply a first scan signal to the first scan lines, second pixels in a second pixel area having a width that is less than a width of the first pixel area, and coupled with second scan lines, second scan stage circuits in a second peripheral area outside the second pixel area, and configured to generate a second scan signal, and first load matching units respectively between the second scan stage circuits, and configured to delay the second scan signal, and to supply the delayed second scan signal to the second scan lines.

Abstract: A display device includes: first pixels in a first pixel region and being connected to first scan lines; second pixels in a second pixel region that is located at a side of the first pixel region and has a width smaller than a width of the first pixel region and being connected to second scan lines; third pixels in a third pixel region that is spaced apart from the second pixel region and has a width smaller than the width of the first pixel region and being connected to third scan lines; a load matching unit in a peripheral region at an outside of the second pixel region and the third pixel region and configured to match loads of the second scan lines and the third scan lines to that of the first scan lines; and a protection unit in the peripheral region and being connected between the second and third pixels and the load matching unit.

Abstract: A display device includes first pixels in a first pixel area and coupled with first scan lines, first scan stage circuits in a first peripheral area outside the first pixel area, and configured to supply a first scan signal to the first scan lines, second pixels in a second pixel area having a width that is less than a width of the first pixel area, and coupled with second scan lines, second scan stage circuits in a second peripheral area outside the second pixel area, and configured to generate a second scan signal, and first load matching units respectively between the second scan stage circuits, and configured to delay the second scan signal, and to supply the delayed second scan signal to the second scan lines.

Abstract: A method of fabricating a solar cell includes forming a doped portion having a first conductive type on a semiconductor substrate, growing an oxide layer on the semiconductor substrate, forming a plurality of recess portions in the oxide layer, further growing the oxide layer on the semiconductor substrate, forming a doped portion having a second conductive type on areas of the semiconductor substrate corresponding to the recess portions, forming a first conductive electrode electrically coupled to the doped portion having the first conductive type, and forming a second conductive electrode on the semiconductor substrate and electrically coupled to the doped portion having the second conductive type, wherein a gap between the doped portions having the first and second conductive types corresponds to a width of the oxide layer formed by further growing the oxide layer.

Abstract: Disclosed is a thin film transistor array panel including: a substrate including a display area and a peripheral area; a second semiconductor layer disposed on the substrate, and disposed on a first semiconductor layer disposed in the display area and the peripheral area; and a passivation layer disposed on the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer include an oxide semiconductor, and a thickness of the first semiconductor layer is different from that of the second semiconductor layer.

Abstract: A manufacturing method of a thin film transistor array panel invention includes forming a semiconductor layer on a substrate including a display area and a peripheral area, arranging a photo mask including a first portion and a second portion having different transmittances from each other, the first portion corresponding to the display area and the second portion corresponding to the peripheral area, and patterning the semiconductor layer to form a first semiconductor disposed in the display area and a second semiconductor disposed in the peripheral area by using the photo mask, in which a thickness of the first semiconductor and a thickness of the second semiconductor are different from each other.

Abstract: A solar cell including a first conductive type semiconductor substrate; a first intrinsic semiconductor layer on a front surface of the semiconductor substrate; a first conductive type first semiconductor layer on at least one surface of the first intrinsic semiconductor layer; a second conductive type second semiconductor layer on a back surface of the semiconductor substrate; a second intrinsic semiconductor layer between the second semiconductor layer and the semiconductor substrate; a first conductive type third semiconductor layer on the back surface of the semiconductor substrate, the third semiconductor layer being spaced apart from the second semiconductor layer; and a third intrinsic semiconductor layer between the third semiconductor layer and the semiconductor substrate.

Abstract: A method of manufacturing a photoelectric device, the method including: forming a first semiconductor layer on a semiconductor substrate through a first ion implantation; forming a second semiconductor layer having an inverted conductive type on a part of the first semiconductor layer through a second ion implantation; and performing thermal processing to restore lattice damage of the semiconductor substrate and activate a dopant into which ion implanted. According to one or more embodiments of the present invention, a photoelectric device having a reduction in the number of processes for manufacturing the photoelectric device and improved output characteristics is provided.

Abstract: A method of fabricating a solar cell includes forming a doped portion having a first conductive type on a semiconductor substrate, growing an oxide layer on the semiconductor substrate, forming a plurality of recess portions in the oxide layer, further growing the oxide layer on the semiconductor substrate, forming a doped portion having a second conductive type on areas of the semiconductor substrate corresponding to the recess portions, forming a first conductive electrode electrically coupled to the doped portion having the first conductive type, and forming a second conductive electrode on the semiconductor substrate and electrically coupled to the doped portion having the second conductive type, wherein a gap between the doped portions having the first and second conductive types corresponds to a width of the oxide layer formed by further growing the oxide layer.

Abstract: A thin film transistor array panel includes: a gate conductor disposed on a substrate and including a gate line and a gate electrode, a semiconductor layer overlapping the gate electrode and including an oxide semiconductor, a data conductor including a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode, a sidewall covering side surface parts of the drain electrode and the source electrode adjacent to a channel region of the semiconductor layer, and a passivation layer covering the source electrode, the drain electrode, and the sidewall.

Abstract: A method of fabricating a solar cell includes forming a doped portion having a first conductive type on a semiconductor substrate, growing an oxide layer on the semiconductor substrate, forming a plurality of recess portions in the oxide layer, further growing the oxide layer on the semiconductor substrate, forming a doped portion having a second conductive type on areas of the semiconductor substrate corresponding to the recess portions, forming a first conductive electrode electrically coupled to the doped portion having the first conductive type, and forming a second conductive electrode on the semiconductor substrate and electrically coupled to the doped portion having the second conductive type, wherein a gap between the doped portions having the first and second conductive types corresponds to a width of the oxide layer formed by further growing the oxide layer.

Abstract: A solar cell including a first conductive type semiconductor substrate; a first intrinsic semiconductor layer on a front surface of the semiconductor substrate; a first conductive type first semiconductor layer on at least one surface of the first intrinsic semiconductor layer; a second conductive type second semiconductor layer on a back surface of the semiconductor substrate; a second intrinsic semiconductor layer between the second semiconductor layer and the semiconductor substrate; a first conductive type third semiconductor layer on the back surface of the semiconductor substrate, the third semiconductor layer being spaced apart from the second semiconductor layer; and a third intrinsic semiconductor layer between the third semiconductor layer and the semiconductor substrate.

Abstract: Disclosed is a thin film transistor array panel including: a substrate including a display area and a peripheral area; a second semiconductor layer disposed on the substrate, and disposed on a first semiconductor layer disposed in the display area and the peripheral area; and a passivation layer disposed on the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer include an oxide semiconductor, and a thickness of the first semiconductor layer is different from that of the second semiconductor layer.

Abstract: A thin film transistor array panel includes: a gate conductor disposed on a substrate and including a gate line and a gate electrode, a semiconductor layer overlapping the gate electrode and including an oxide semiconductor, a data conductor including a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode, a sidewall covering side surface parts of the drain electrode and the source electrode adjacent to a channel region of the semiconductor layer, and a passivation layer covering the source electrode, the drain electrode, and the sidewall.

Abstract: A photoelectric device includes a first semiconductor structure and a second semiconductor structure on a substrate, and the first semiconductor structure includes a different conductivity type from the second semiconductor structure. The photoelectric device also includes a first electrode on the first semiconductor structure and a second electrode on the second semiconductor structure, and an interlayer insulating structure adjacent to the second semiconductor structure. The interlayer insulating structure separates the first semiconductor structure from the second semiconductor structure and separates the first semiconductor structure from the second electrode.

Abstract: A photoelectric device includes: a semiconductor substrate including monocrystalline silicon and has first and second surfaces that are opposite to each other; a doping unit formed on the first surface of the semiconductor substrate; and an insulating layer that is formed between the doping unit and the second surface of the semiconductor substrate, wherein the doping unit includes: a first semiconductor layer including a first dopant doped in the monocrystalline silicon; and a second semiconductor layer including a second dopant doped in the monocrystalline silicon.

Abstract: A method of manufacturing a photoelectric device, the method including: forming a first semiconductor layer on a semiconductor substrate through a first ion implantation; forming a second semiconductor layer having an inverted conductive type on a part of the first semiconductor layer through a second ion implantation; and performing thermal processing to restore lattice damage of the semiconductor substrate and activate a dopant into which ion implanted. According to one or more embodiments of the present invention, a photoelectric device having a reduction in the number of processes for manufacturing the photoelectric device and improved output characteristics is provided.

Abstract: A method of fabricating a solar cell includes forming a doped portion having a first conductive type on a semiconductor substrate, growing an oxide layer on the semiconductor substrate, forming a plurality of recess portions in the oxide layer, further growing the oxide layer on the semiconductor substrate, forming a doped portion having a second conductive type on areas of the semiconductor substrate corresponding to the recess portions, forming a first conductive electrode electrically coupled to the doped portion having the first conductive type, and forming a second conductive electrode on the semiconductor substrate and electrically coupled to the doped portion having the second conductive type, wherein a gap between the doped portions having the first and second conductive types corresponds to a width of the oxide layer formed by further growing the oxide layer.

Abstract: A solar cell includes a semiconductor substrate, a first intrinsic semiconductor layer and a second intrinsic semiconductor layer on the semiconductor substrate, the first intrinsic semiconductor layer and the second intrinsic semiconductor layer being spaced apart from each other, a first conductive semiconductor layer and a second conductive semiconductor layer respectively disposed on the first intrinsic semiconductor layer and the second intrinsic semiconductor layer, and a first electrode and a second electrode, each including a bottom layer on the first conductive semiconductor layer and the second conductive semiconductor layer, respectively, the bottom layer including a transparent conductive oxide, and an intermediate layer on the bottom layer, the intermediate layer being including copper.