Abstract: A portable display device includes a display panel displaying an image with pixels of a display area, a touch sensor disposed in a front surface direction of the display area and a non-display area of the display panel, a touch driving circuit driving touch electrodes of the touch sensor to detect a touch occurrence position of at least one point, a touch movement direction, and a movement distance and generating touch coordinate data according to a detection result, and a display driving circuit displaying an icon or a menu bar in the display area so that a user controls a screen control function and an operation control function of the display panel according to the touch occurrence position of the at least one point, the touch movement direction, and the movement distance.

Abstract: A coil component includes a body, a support member disposed within the body, a coil disposed on at least one of a first surface and a second surface of the support member opposing each other, and an external electrode disposed on the body and connected to the coil, wherein the support member includes a first layer and a second layer respectively including polyimide, and an average surface roughness of the surface of the support member on which the coil is disposed is 0.1 to 0.5 ?m in Ra value.

Abstract: The present invention relates to a water purifier provided with a composite filter, and more particularly, to a water purifier provided with a composite filter, which enables the implementation of an additional function using an external treatment member in a process in which raw water passes through a composite filter as the water purifier cannot only receive raw water, discharge second purified water, receive externally treated water, discharge third purified water, but also discharge residential water.

Abstract: A multilayer circuit board including a ceramic substrate part and a unit circuit board coupled to one surface of the ceramic substrate part. The unit circuit board includes an insulating layer with a circuit pattern formed on one side, an adhesive layer adhered to another surface of the insulating layer, a via hole passing through the insulating layer and the adhesive layer and connected to one surface of the circuit pattern, and conductive paste filled in the via hole. A manufacturing method including batch bonding a circuit board part, which includes a plurality of unit circuit boards, and a ceramic substrate part, wherein each unit circuit board includes providing an insulating layer having a circuit layer, forming an adhesive layer on the insulating layer, forming a circuit pattern, forming a via hole in the insulating and adhesive layers, and filling the via hole with conductive paste.

Abstract: A semiconductor device is provided. The semiconductor device includes a first wiring and a second wiring disposed at a first metal level, a third wiring and a fourth wiring disposed at a second metal level different from the first metal level, a first via which directly connects the first wiring and the third wiring, a fifth wiring disposed at a third metal level between the first metal level and the second metal level and connected to the second wiring, and a second via which directly connects the fourth wiring and the fifth wiring.

Abstract: A semiconductor device includes a plurality of main contact plugs and a plurality of dummy contact plugs which pass through an insulating layer on a substrate. A plurality of upper interconnections is on the insulating layer. The plurality of dummy contact plugs include a first dummy contact plug. The plurality of upper interconnections include a first upper interconnection overlapping the first dummy contact plug. A vertical central axis of the first dummy contact plug is located outside the first upper interconnection.

Abstract: A method of manufacturing a semiconductor device may include forming a hardmask layer on a substrate, forming a first mold pattern on the hardmask layer using a first photolithography process, conformally forming a spacer layer on the first mold pattern and on portions of the hardmask layer exposed by the first mold pattern, forming a first mold layer using a second photolithography process. The first mold layer may have a first opening that exposes a portion of the spacer layer. The method may include forming a spacer pattern by anisotropically etching the portion of the spacer layer exposed by the first opening until a portion of a top surface of the hardmask layer is exposed, and using the spacer pattern as an etching mask to pattern the hardmask layer.

Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer.

Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a first wiring and a second wiring disposed at a first metal level, a third wiring and a fourth wiring disposed at a second metal level different from the first metal level, a first via which directly connects the first wiring and the third wiring, a fifth wiring disposed at a third metal level between the first metal level and the second metal level and connected to the second wiring, and a second via which directly connects the fourth wiring and the fifth wiring.

Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer.

Abstract: A method of manufacturing a semiconductor device may include forming a hardmask layer on a substrate, forming a first mold pattern on the hardmask layer using a first photolithography process, conformally forming a spacer layer on the first mold pattern and on portions of the hardmask layer exposed by the first mold pattern, forming a first mold layer using a second photolithography process. The first mold layer may have a first opening that exposes a portion of the spacer layer. The method may include forming a spacer pattern by anisotropically etching the portion of the spacer layer exposed by the first opening until a portion of a top surface of the hardmask layer is exposed, and using the spacer pattern as an etching mask to pattern the hardmask layer.

Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer.

Abstract: A semiconductor device includes a plurality of main contact plugs and a plurality of dummy contact plugs which pass through an insulating layer on a substrate. A plurality of upper interconnections is on the insulating layer. The plurality of dummy contact plugs include a first dummy contact plug. The plurality of upper interconnections include a first upper interconnection overlapping the first dummy contact plug. A vertical central axis of the first dummy contact plug is located outside the first upper interconnection.

Abstract: A non-volatile memory device includes a data storage structure coupled between first and second conductive lines of the memory device. The data storage structure includes a conductive lower heater element, a data storage pattern, and a conductive upper heater element sequentially stacked. At least one sidewall surface of the data storage pattern is coplanar with a sidewall surface of the upper heater element thereabove and a sidewall surface of the lower heater element therebelow. Related fabrication methods are also discussed.

Abstract: A diode may be formed within a molding layer on a substrate. A conductive buffer pattern having a greater planar area than the diode may be on the diode and molding layer. An electrode structure may be on the conductive buffer pattern. A data storage pattern may be on the electrode structure. One lateral surface of the conductive buffer pattern may be vertically aligned with one lateral surface of the electrode structure.

Abstract: A phase-change memory device includes a diode, a plug, a doping layer pattern, a phase-change layer pattern and an upper electrode. The diode is disposed on a substrate. The plug is disposed on the diode and has a bottom surface whose area is equal to the area of a top surface of the diode. The plug is formed of metal or a conductive metallic compound. The doping layer pattern is disposed on the plug and has a bottom surface whose area is equal to the area of a top surface of the plug, and includes the same metal or conductive metallic compound as the plug. The phase-change layer pattern is disposed on the doping layer pattern. The upper electrode is disposed on the phase-change layer pattern.

Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.

Abstract: A sacrificial pattern is formed to partially cover the pipe-shaped electrode. A sacrificial spacer is formed on a lateral surface of the sacrificial pattern. The sacrificial spacer extends across the pipe-shaped electrode. The sacrificial spacer has a first side and a second side opposite the first side. The sacrificial pattern is removed to expose the pipe-shaped electrode proximal to the first and second sides of the sacrificial spacer. The pipe-shaped electrode exposed on both sides of the sacrificial spacer may be primarily trimmed. The pipe-shaped electrode is retained under the sacrificial spacer to form a first portion, and a second portion facing the first portion. The second portion of the pipe-shaped electrode is secondarily trimmed. The sacrificial spacer is removed to expose the first portion of the pipe-shaped electrode. A data storage plug is formed on the first portion of the pipe-shaped electrode.

Abstract: A phase change memory device includes an impurity region on a substrate, the impurity region being in an active region, a metal silicide pattern at least partially buried in the impurity region, a diode on the impurity region, a lower electrode on the diode, a phase change layer pattern on the lower electrode, and an upper electrode on the phase change layer pattern.