Abstract: A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.

Abstract: A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.

Abstract: A semiconductor device includes first and second trenches in respective first and second regions in a substrate, a first isolation structure having a first inner wall oxide pattern, a first liner, and a first filling insulation pattern sequentially stacked I the first trench, a second isolation structure having a second inner wall oxide pattern, a second liner, and a second filling insulation pattern sequentially stacked I the second trench, a first gate structure having a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked on the first region, and a second gate structure having a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked on the second region, wherein the first and second liners protrude above upper surfaces of the first and second inner wall oxide patterns and the first and second filling insulation patterns, respectively.

Abstract: A semiconductor device includes first and second trenches in respective first and second regions in a substrate, a first isolation structure having a first inner wall oxide pattern, a first liner, and a first filling insulation pattern sequentially stacked I the first trench, a second isolation structure having a second inner wall oxide pattern, a second liner, and a second filling insulation pattern sequentially stacked I the second trench, a first gate structure having a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked on the first region, and a second gate structure having a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked on the second region, wherein the first and second liners protrude above upper surfaces of the first and second inner wall oxide patterns and the first and second filling insulation patterns, respectively.

Abstract: A semiconductor memory device may have a substrate including an active region in a memory cell region and a logic active region in a peripheral region, an element isolation structure between the active region and the logic active region, an insulating layer pattern covering the active region, and a support insulating layer. The insulating layer pattern may include an extension portion that extends along the element isolation structure, may be spaced apart from the element isolation structure, and may overhang over the element isolation structure. The support insulating layer may fill a recess space defined between the extension portion and the element isolation structure.

Abstract: A semiconductor device includes first and second trenches in respective first and second regions in a substrate, a first isolation structure having a first inner wall oxide pattern, a first liner, and a first filling insulation pattern sequentially stacked I the first trench, a second isolation structure having a second inner wall oxide pattern, a second liner, and a second filling insulation pattern sequentially stacked I the second trench, a first gate structure having a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked on the first region, and a second gate structure having a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked on the second region, wherein the first and second liners protrude above upper surfaces of the first and second inner wall oxide patterns and the first and second filling insulation patterns, respectively.

Abstract: A semiconductor device includes a substrate having first and second active patterns therein, which are spaced apart from each other. The first active pattern has a top surface that is elevated relative to a top surface of the second active pattern. A channel semiconductor layer is provided on the top surface of the first active pattern. A first gate pattern is provided, which includes a first insulating pattern, on the channel semiconductor layer. A second gate pattern is provided, which includes a second insulating pattern having a thickness greater than a thickness of the first insulating pattern, on the top surface of the second active pattern.

Abstract: A semiconductor device includes a substrate, a gate dielectric layer on the substrate, the gate dielectric layer including a recess at a side surface thereof, a gate electrode structure on the gate dielectric layer, a gate capping layer on the gate electrode structure, and a spacer structure on the substrate and covering side surfaces of the gate dielectric layer, the gate electrode structure, and the gate capping layer, the spacer structure including a first spacer, a second spacer on the first spacer and covering the recess, and a third spacer on the second spacer, the second spacer and the third spacer including silicon nitride.

Abstract: Aspects of the present disclosure involve systems, methods, and the like, for a fabrication of a particulate matter (PM) sensor that utilizes a capacitance sensor to detect sub-micrometer and nanoparticles in the respirable range of an environment. In one implementation, the capacitance sensor may comprise interdigitated electrodes between which a capacitance may be measured. PM deposited on the sensor may cause the capacitance between the electrodes to be altered and such a change in capacitance may be measured by the PM sensor. This measurement of the change in capacitance of the interdigitated capacitance sensor may therefore be correlated to the presence of sub-micrometer and nanoparticles in an environment. In one particular implementation, the PM sensor may further include a micro-heater circuit, a readout circuit, and an interface connecting the readout circuit to the micro-heater/capacitance sensor of the PM sensor.

Abstract: A semiconductor device including a gate structure on a substrate, a first gate spacer, and a second gate spacer may be provided. A sidewall of the gate structure includes a concave lower sidewall portion and an upper sidewall portion that is vertical with respect to an upper surface of the substrate. The first gate spacer is formed on the upper sidewall portion of the sidewall of the gate structure. The second gate spacer is formed on the concave lower sidewall portion of the sidewall of the gate structure and an outer sidewall of the first gate spacer. The second gate spacer contacts a lower surface of the first gate spacer and includes nitride.

Abstract: Disclosed is a semiconductor device comprising a peripheral word line disposed on a substrate, a lower dielectric pattern covering the peripheral word line and including a first part that covers a lateral surface of the peripheral word line and a second part that covers a top surface of the peripheral word line, a contact plug on one side of the peripheral word line and penetrating the first and second parts, and a filling pattern in contact with the second part of the lower dielectric pattern and penetrating at least a portion of the second part. The contact plug includes a contact pad disposed on a top surface of the lower dielectric pattern, and a through plug penetrating the first and second parts. The filling pattern surrounds a lateral surface of the contact pad. The first and second parts include the same material.

Abstract: A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.

Abstract: A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.

Abstract: A semiconductor device includes first and second trenches in respective first and second regions in a substrate, a first isolation structure having a first inner wall oxide pattern, a first liner, and a first filling insulation pattern sequentially stacked I the first trench, a second isolation structure having a second inner wall oxide pattern, a second liner, and a second filling insulation pattern sequentially stacked I the second trench, a first gate structure having a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked on the first region, and a second gate structure having a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked on the second region, wherein the first and second liners protrude above upper surfaces of the first and second inner wall oxide patterns and the first and second filling insulation patterns, respectively.

Abstract: A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.

Abstract: A semiconductor memory device may have a substrate including an active region in a memory cell region and a logic active region in a peripheral region, an element isolation structure between the active region and the logic active region, an insulating layer pattern covering the active region, and a support insulating layer. The insulating layer pattern may include an extension portion that extends along the element isolation structure, may be spaced apart from the element isolation structure, and may overhang over the element isolation structure. The support insulating layer may fill a recess space defined between the extension portion and the element isolation structure.

Abstract: Aspects of the present disclosure involve systems, methods, and the like, for a fabrication of a particulate matter (PM) sensor that utilizes a capacitance sensor to detect sub-micrometer and nanoparticles in the respirable range of an environment. In one implementation, the capacitance sensor may comprise interdigitated electrodes between which a capacitance may be measured. PM deposited on the sensor may cause the capacitance between the electrodes to be altered and such a change in capacitance may be measured by the PM sensor. This measurement of the change in capacitance of the interdigitated capacitance sensor may therefore be correlated to the presence of sub-micrometer and nanoparticles in an environment. In one particular implementation, the PM sensor may further include a micro-heater circuit, a readout circuit, and an interface connecting the readout circuit to the micro-heater/capacitance sensor of the PM sensor.