Abstract: The present specification relates to an organic-inorganic hybrid solar cell.

Abstract: The present specification relates to an organic solar cell and a method for manufacturing the same.

Abstract: The present specification relates to an organic solar cell and a method for manufacturing the same.

Abstract: The present specification relates to a heterocyclic compound and an organic solar cell including the same.

Abstract: The present specification relates to an organic electronic device including a fullerene derivative.

Abstract: The present specification provides a copolymer and an organic solar cell including the same.

Abstract: The present specification provides a copolymer and an organic solar cell including the same.

Abstract: Asynchronous-synchronous digital signal conversion and vice versa are realized by employing a single synchronizing elastic store and associated phase detector. The signal smoothing and synchronization processes are achieved with a single elastic store by low pass filtering the elastic store write-read address separation signal from the phase detector to obtain a smooth stuff control signal. In turn, the smooth stuff control signal is employed to make a stuff decision for controlling the elastic store read clock signal. In a specific embodiment the low pass filtering is realized by first synchronously sampling the write-read address separation signal and, then, employing a digital low pass filter to obtain the aliasing free smooth stuff control signal.

Abstract: An output timing signal is generated by a phase locked loop. The loop includes a phase detector, a low-pass filter and a voltage controlled oscillator. A reference signal that is in synchronism with an incoming digital signal is divided by a first divisor to generate a reference clock signal. The reference clock signal is supplied as a first input to the phase detector. A phase clock signal is generated in the loop by dividing the output timing signal by a second predetermined divisor. The phase clock signal is supplied as a second input to the phase detector to generate an error signal for controlling the oscillator. The first and second divisors are selected to eliminate jitter caused by large gaps in the incoming digital signal resulting from overhead bit removal. Additionally, the phase clock signal is controllably compensated to cause variations in the bit rate of the output timing signal which correspond to variations in the actual data rate of the incoming digital signal because of stuffing bits.

Abstract: A desired positive fractional stuffing ratio is obtained in a frame synchronizer for a digital signal having a channel frame format that included two stuffing bit positions to obtain either positive or negative stuffing. The fractional stuffing ratio is obtained by controllably increasing the duration of a first predetermined number of intervals during which data bits are written into the synchronizer and, then, by controllably decreasing the duration of a second predetermined number of intervals during which data bits are written into the synchronizer. A data bit is forced to be included in one of the stuffing bit positions occurring during each of the first predetermined number of intervals and a non-data bit is forced to be included in one of the stuffing bit positions occurring during each of the second predetermined number of intervals.