Abstract: A display device having a plurality of select lines includes redundant select line scanners. Each scanner includes a plurality of substantially identical stages having an input terminal and an output terminal. The stages and select lines are ordinally numbered and correspondingly numbered stages are connected to opposite ends of the correspondingly numbered select lines by separate line segments. The stages within each scanner are cascaded by connecting the output terminal of each stage to the input terminal of the immediately succeeding stage. Failed stages of a scanner are replaced by the correspondingly numbered stage of the other scanner simply by opening the separate line segment of the failed stage.

Abstract: A video display driver applies a video signal to column electrodes of a liquid crystal display. The display driver includes a reference ramp generator and column data line drivers. Each data line driver includes a switching arrangement coupled to a first capacitance for storing a portion of the video signal in the first capacitance. A first terminal of the first capacitance is coupled to the reference ramp generator for combining a reference ramp signal with the stored video signal and for applying the combined signal to an input of a comparator. The comparator controls a transistor that couples a data ramp signal to a given column of the pixels. The reference ramp generator is coupled to the input of the comparator in a non-switched manner such that no switching transistor is interposed in a signal path between the reference ramp generator and the input of the comparator.

Abstract: A data driver circuit and system driving scheme that can be integrated directly onto an LCD display substrate to reduce the cost of the peripheral integrated circuits and the hybrid assembly needed by unscanned active matrix liquid crystal displays to connect them to the array. A demultiplexer circuit is deposited on the display for demultiplexing a group of Y columns of multiplexed video data input signals to X groups of Y pixel capacitors that are also deposited on the substrate in Z rows. In addition, a data driver circuit provides voltage signals to precharge the pixel capacitors to a first voltage level in a first time period such that video data input signals coupled thereto in a multiplexed fashion during a second time period causes the pixel capacitors to store to a second predetermined voltage level to provide a video display as the rows of pixels are sequentially scanned.

Abstract: A data line defect avoidance structure for a display device having an array of display elements arranged in rows and columns includes a plurality of repair lines overlapping the ends of data lines which extend between the columns. Each repair line spans a set of data lines, and there is a sufficient number of repair lines to span all the data lines in the array. One end of each repair line can be welded to a data line during fabrication to decrease the number of steps required for avoiding an open in a data line.

Abstract: A display device having a plurality of select lines includes redundant select line scanners. Each scanner includes a plurality of substantially identical stages having an input terminal and an output terminal. The stages and select lines are ordinally numbered and correspondingly numbered stages are connected to opposite ends of the correspondingly numbered select lines by separate line segments. The stages within each scanner are cascaded by connecting the output terminal of each stage to the input terminal of the immediately succeeding stage. The select line scanners are independently operable by the provision separate power supplies and clock generators. During testing, one scanner is made to look like a high impedance to the scanner being tested. Failed stages of a scanner are replaced by the correspondingly numbered stage of the other scanner simply by opening the separate line segment of the failed stage.

Abstract: A select line scanner for a liquid crystal display includes a plurality of cascaded stages each having an input terminal and an output terminal. Each stage includes an output circuit which switches the output terminal between high and low states. A first node switches the output terminal in response to an input signal and a second node keeps the output terminal low between the input pulse and a clocking pulse.

Abstract: A system for applying brightness signals to the pixels of a display device includes a transmission gate for each column of pixels. The control electrodes of the transmission gates are precharged to the threshold voltage of the gates to substantially increase the speed of the system. Comparators compare brightness voltages to a reference ramp voltage to enhance the speed and accuracy of the system.

Abstract: A shift register includes transistors having conduction paths serially connected at a node and between an input terminal receiving a constant voltage and a clocked terminal receiving a clocked voltage of a first phase. The control electrode of one of the transistors receives a clocked voltage of a second phase and the control electrode of the other transistor receives an input signal. An inverter is arranged between the node and the output terminal.

Abstract: A circuit for testing a liquid crystal display for open data lines, for identifying select lines shorted to data lines, and for identifying failed data line scanner stages includes thin film transistors arranged between each data line and a segmented bus. A sectioned shift register sequentially actuates the thin film transistors and the bus segments are monitored while data signals are applied to the data lines. The absence of a voltage on the bus indicates an open data line. The bus is also monitored while select signals are applied to the select lines and the shift register sequentially actuates the thin film transistors, the presence of a voltage on the bus indicates a short between a data line and a select line.

Abstract: A select line scanner circuit for a display device has a plurality of register stages. The register stages each include first and second register segments and first and second latch circuit means which receive select signals and apply oppositely poled logic signals to the output nodes of the register stages. Voltage boosting means are associated with at lest one of the register stages to assure that the logic signals are applied at the proper levels.

Abstract: A liquid crystal pixel electrode and a thin film transistor (TFT) structure includes a select line, a portion of which is coated with undoped solid state material. The select line is parallel to a continuous uninterrupted side of the pixel electrode and a data line is parallel to another continuous uninterrupted side of the pixel electrode. A source area and a drain area of doped solid state material are placed over the undoped layer. The source area contacts the data line and the drain area contacts the pixel electrode. The select line also serves as the gate electrode of the TFT. A notch passes through the undoped material between the data line and the drain to prevent leakage.

Abstract: A memory cell structure has a pair of cross-coupled inverters, each inverter having first and second MOS series coupled transistors. Each of the second inverter transistors has a source disposed near the periphery of the cell, a drain disposed closer to the center of the cell than the source thereof, and a channel region disposed between the source and drain. The channel region shields the sensitive drain from radiation generated photocurrents, thereby minimizing the chance of a change in logic state during radiation.

Abstract: A semiconductor device comprising an island of semiconductor material disposed on an insulating substrate is disclosed. A MOS transistor is formed in the semiconductor material, but the gate electrode does not extend over any sidewall of the silicon island. In order to electrically isolate the source and drain regions in the areas of the silicon island not subtended by the gate electrode, a pair of diodes in series is used to eliminate the shorting paths.

Abstract: A memory cell structure has a thin insulating oxide barrier layer between an insulating body, such as sapphire, and a conducting layer, such as polysilicon, to prevent photoconduction between the body and the layer. Upper and lower conducting layers form a capacitor with a source and a drain in the lower layer and a gate in the upper layer to isolate the sensitive gate from a substrate during photoconduction. These features help the cell resist a radiation-induced logic state change.

Abstract: Integrated latch circuitry for driving row or column busses of a matrix device fabricated in low mobility semiconductor material includes cross coupled transistors having variable impedance load devices. The cross coupled transistors are coupled between relatively positive and relatively negative supply potentials. The relatively negative supply potential is modulated to preset the state of the latches in order to reduce the load on input circuitry applying data to the latch. The variable impedance loads are modulated between relatively high and relatively low impedances to enhance the speed at which the latches change state.

Abstract: A radiation hard memory cell comprises on an insulating substrate a low output impedance inverter made of a monocrystalline semiconductor and a high output impedance inverter made of a non-crystalline semiconductor in order to save space. The semiconductor can be Si and a barrier layer can be used. A method for making the cell comprises depositing and defining active layers, making gate insulating layers on the active layers, forming gates on the insulating layers, and forming source and drain regions in the active layers. One inverter can have its active and insulating layers formed before the remaining active layer is formed. The remaining active layer can then be simultaneously formed with the gate of the one active layer.

Abstract: A common island complementary-metal-oxide semiconductor device comprising an island of semiconductor material disposed on an insulating substrate is disclosed. Both N-channel and P-Channel transistors are formed in the common island of semiconductor material, but the gate electrode does not extend over the sidewalls of the silicon island. In order to electrically isolate the source and drain regions for each transistor, the areas of the silicon island outside of the channel region are doped with the appropriate dopants to form back-to-back diodes in series with respect to the source and drain regions. Additionally, a diode is disposed between both the N-channel and P-channel transistors to electrically isolate the two transistors.

Abstract: A memory cell circuit has a pair of inverters and a means, such as gate-drain coupled capacitors, for providing a greater voltage difference at MOS transistor gates during radiation than an initial value. This tends to preserve the latch logic state and thus prevent a change in logic state during radiation.

Abstract: A semiconductor device comprising an island of semiconductor material disposed on an insulating substrate is disclosed. A MOS transistor is formed in the semiconductor island such that the gate electrode extends over the sidewalls of the island. Diodes are formed between the source and drain regions and the portions of the channel region along the sidewalls to electrically isolate the top transistor from the parasitic edge transistors.

Abstract: A semiconductor device having a layer of semiconductor material disposed on an insulating substrate is disclosed. Source and drain depth extenders are provided within the semiconductor material for extending the respective source and drain regions to the insulating substrate. This device is fabricated in a manner which minimizes damage to the gate oxide layer that often occurs when high energy implants are used to form self-aligned source and drain regions.