Patents by Inventor Dorai Iyer

Dorai Iyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of making an insulated gate semiconductor device with source-substrate connection and structure
    Patent number: 8471331
    Abstract: In one embodiment, a source-down vertical insulated gate field effect transistor includes a source contact that is buried within a trench gate structure. Dopant of a first conductivity type is diffused from the conductive source contact into an adjacent semiconductor layer that has a second and opposite conductivity type to form source regions. A self-aligned metal contact is formed within the trench gate structure to short the source contact and the source regions to an underlying substrate.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: June 25, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Dorai Iyer, Gordon M. Grivna, Jeffrey Pearse
  • METHOD OF MAKING AN INSULATED GATE SEMICONDUCTOR DEVICE WITH SOURCE-SUBSTRATE CONNECTION AND STRUCTURE
    Publication number: 20130043526
    Abstract: In one embodiment, a source-down vertical insulated gate field effect transistor includes a source contact that is buried within a trench gate structure. Dopant of a first conductivity type is diffused from the conductive source contact into an adjacent semiconductor layer that has a second and opposite conductivity type to form source regions. A self-aligned metal contact is formed within the trench gate structure to short the source contact and the source regions to an underlying substrate.
    Type: Application
    Filed: August 15, 2011
    Publication date: February 21, 2013
    Inventors: Dorai Iyer, Gordon M. Grivna, Jeffrey Pearse