Abstract: In accordance with the teachings described herein, systems and methods are provided for reducing the lock time of a phase locked loop circuit. A phase comparator may be used to detect a phase error between an input reference signal and a feedback clock signal. A frequency synthesizer circuit may be used to control the frequency of an output clock signal as a function of the phase error between the input signal and the feedback clock signal. A feedback divider may be used to divide the frequency of the output clock signal to generate the feedback clock signal. A phase error monitor may be used to detect when the phase error between the input signal and the feedback clock signal reaches a peak value, and in response to detecting the peak value, initialize the feedback divider to reduce the phase error between the input signal and the feedback clock signal.