Abstract: An image capture unit has mounted in a frame: a first imaging assembly, a first circuit board, a second imaging assembly, and a second circuit board. The first imaging assembly is mounted on the first circuit board. The second imaging assembly is mounted on the second circuit board. A portion of the first circuit board and a portion of the second circuit board have a stacked configuration with the portion of the first circuit board being approximately parallel to the portion of the second circuit board. An end of another portion of the first circuit board is adjacent to an end of another portion of the second circuit board.

Abstract: A resolution detector may be used in conjunction with an ADC to identify unresolved bits in a raw digital output of the ADC. Bits that have been properly resolved by the ADC may be distinguished from those that have not been successfully resolved, because of time limitations or other reasons. Each bit that has not been successfully resolved may be classified and referred to as an unresolved bit. If there are any unresolved bits detected in a sampling cycle, dither may then be incorporated in the raw digital output to compensate for the unresolved bits in that cycle. The dither may be added to the raw digital output of the ADC to eliminate any missing codes in the processed digital output codes or the dither may be substituted for the unresolved bits in raw digital output to generate the processed digital output.

Abstract: A tracking module that tracks the operation of a digital-to-analog converter (DAC). The DAC tracking module may be included on-chip with a DAC, and be formed with similar circuit components as a DAC. The DAC tracking circuit may output a signal indicating that the DAC within a SAR ADC has settled to an approximate value during each bit conversion. A differential solution is also provided. Power may be optimized because optimal conversion speed may be achieved, and a comparator within the DAC may be turned off or placed in a standby mode at the end of bit conversions, and before the next conversion cycle in response to the signal output by the DAC tracking module.

Abstract: A resolution detector may be used in conjunction with an ADC to identify unresolved bits in a raw digital output of the ADC. Bits that have been properly resolved by the ADC may be distinguished from those that have not been successfully resolved, because of time limitations or other reasons. Each bit that has not been successfully resolved may be classified and referred to as an unresolved bit. If there are any unresolved bits detected in a sampling cycle, dither may then be incorporated in the raw digital output to compensate for the unresolved bits in that cycle. The dither may be added to the raw digital output of the ADC to eliminate any missing codes in the processed digital output codes or the dither may be substituted for the unresolved bits in raw digital output to generate the processed digital output.

Abstract: A tracking module that tracks the operation of a digital-to-analog converter (DAC). The DAC tracking module may be included on-chip with a DAC, and be formed with similar circuit components as a DAC. The DAC tracking circuit may output a signal indicating that the DAC within a SAR ADC has settled to an approximate value during each bit conversion. A differential solution is also provided. Power may be optimized because optimal conversion speed may be achieved, and a comparator within the DAC may be turned off or placed in a standby mode at the end of bit conversions, and before the next conversion cycle in response to the signal output by the DAC tracking module.

Abstract: Devices and methods for varying individual periods or cycle times of upconverted clock signals within a corresponding reference clock cycle are disclosed. In some embodiments, these varying cycle times may improve signal synchronization between the upconverted clock and the reference clock. In different embodiments, different types of counters and counting circuits keep track of the number of elapsed upconverted clock cycles in order to determine the specific upconverted clock cycles with longer cycle times. In some embodiments, a signal may be sent to a delay line to change the amount of delay between upconverted clock pulses, thereby increasing or decreasing a specific upconverted clock cycle time or period. In some embodiments the specific upconverted clock cycle(s) changed in each reference clock cycle may vary, which may further improve reconciliation between the upconverted clock cycles and the corresponding reference clock cycle.

Abstract: Some embodiments provide real-time variable delays in a delay line. In some of these embodiments, the real-time variable delays may be enable without producing clock glitches. In an embodiment, delay cells in a delay line may be coupled together in a chain to form a lattice of inverters providing different paths of signal propagation. Each path may have a different number of inverters; each inverter adding a known processing time associated with the signal inversion process. In some embodiments, an input signal may be propagated in an inverted or non-inverted form to the inputs of multiple inverters in the lattice, including the inputs of inverters through which the input signal does not propagate. A desired delay time may be obtained in an embodiment by selecting a path containing a desired number and configuration of inverters. The path may be selected in an embodiment using switchably enabled inverters.

Abstract: Devices and methods for varying individual periods or cycle times of upconverted clock signals within a corresponding reference clock cycle are disclosed. In some embodiments, these varying cycle times may improve signal synchronization between the upconverted clock and the reference clock. In different embodiments, different types of counters and counting circuits keep track of the number of elapsed upconverted clock cycles in order to determine the specific upconverted clock cycles with longer cycle times. In some embodiments, a signal may be sent to a delay line to change the amount of delay between upconverted clock pulses, thereby increasing or decreasing a specific upconverted clock cycle time or period. In some embodiments the specific upconverted clock cycle(s) changed in each reference clock cycle may vary, which may further improve reconciliation between the upconverted clock cycles and the corresponding reference clock cycle.

Abstract: Some embodiments provide real-time variable delays in a delay line. In some of these embodiments, the real-time variable delays may be enable without producing clock glitches. In an embodiment, delay cells in a delay line may be coupled together in a chain to form a lattice of inverters providing different paths of signal propagation. Each path may have a different number of inverters; each inverter adding a known processing time associated with the signal inversion process. In some embodiments, an input signal may be propagated in an inverted or non-inverted form to the inputs of multiple inverters in the lattice, including the inputs of inverters through which the input signal does not propagate. A desired delay time may be obtained in an embodiment by selecting a path containing a desired number and configuration of inverters. The path may be selected in an embodiment using switchably enabled inverters.