Patents by Inventor Doron Orenstlen

Doron Orenstlen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Selective hardware lock disabling
    Patent number: 7975129
    Abstract: Controlling a reorder buffer (ROB) to selectively perform functional hardware lock disabling (HLD) is described. One apparatus embodiment includes a unit to enable an ROB to selectively disable a lock upon Identifying a lock acquire operation (LAO) associated with a critical section (CS) entry point, a unit to selectively retire the LAO, a unit to cause the ROB to selectively disable the lock, and a unit to snoop a buffer. The apparatus may, based on the snooping, selectively abort a transaction associated with the CS.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: July 5, 2011
    Assignee: Intel Corporation
    Inventors: Shlomo Raikin, Gad Sheaffer, Doron Orenstlen
  • Selective Hardware Lock Disabling
    Publication number: 20100011193
    Abstract: Controlling a reorder buffer (ROB) to selectively perform functional hardware lock disabling (HLD) is described. One apparatus embodiment includes a unit to enable an ROB to selectively disable a lock upon Identifying a lock acquire operation (LAO) associated with a critical section (CS) entry point, a unit to selectively retire the LAO, a unit to cause the ROB to selectively disable the lock, and a unit to snoop a buffer. The apparatus may, based on the snooping, selectively abort a transaction associated with the CS.
    Type: Application
    Filed: September 18, 2009
    Publication date: January 14, 2010
    Inventors: Shlomo Raikin, Gad Sheaffer, Doron Orenstlen
  • METHOD AND APPARATUS FOR A DOUBLE WIDTH LOAD USING A SINGLE WIDTH LOAD PORT
    Publication number: 20090164763
    Abstract: A single micro-instruction to perform either an N-bit or a 2N-bit load is provided. A microprocessor having an N-bit load port performs either an N-bit load or a 2N-bit load in a single cycle with the same micro-instruction being used for both the N-bit and the 2N-bit load.
    Type: Application
    Filed: December 21, 2007
    Publication date: June 25, 2009
    Inventors: Zeev Sperber, Robert Valentine, Ehud Cohen, Doron Orenstlen, Benny Eitan