Patents by Inventor Doron Rajwan

Doron Rajwan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Adjusting power consumption of a processing element based on types of workloads to be executed
    Patent number: 9652018
    Abstract: Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Alon Naveh, Eliezer Weissmann
  • Dynamically Optimizing Power Management Operational Parameters Of A Processor
    Publication number: 20170131754
    Abstract: In one embodiment, a processor includes at least one core, at least one thermal sensor, and a power controller including a first logic to dynamically update a time duration for which the at least one core is enabled to be in a turbo mode. Other embodiments are described and claimed.
    Type: Application
    Filed: November 10, 2015
    Publication date: May 11, 2017
    Inventors: Shmuel Zobel, Maxim Levit, Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Dorit Shapira, Nadav Shulman
  • Controlling a turbo mode frequency of a processor
    Patent number: 9618997
    Abstract: In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: April 11, 2017
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Ryan Wells, Nadav Shulman
  • Enabling A Non-Core Domain To Control Memory Bandwidth
    Publication number: 20170097668
    Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.
    Type: Application
    Filed: December 16, 2016
    Publication date: April 6, 2017
    Inventors: Avinash N. Ananthakrishnan, Inder M. Sodhi, Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Ryan Wells
  • TECHNIQUES FOR FLEXIBLE AND DYNAMIC FREQUENCY-RELATED TELEMETRY
    Publication number: 20170090945
    Abstract: Methods and apparatus relating to techniques for flexible and/or dynamic frequency-related telemetry are described. In an embodiment, logic, coupled to a processor, communicates information to a module. The communicated information includes a duration counter value corresponding to a duration in which an operating characteristic of the processor is controlled. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Applicant: Intel Corporation
    Inventors: Doron Rajwan, Eliezer Weissmann, Yoni Aizik, Itai Feit, Tal Kuzi, Tomer Ziv, Nadav Shulman
  • SYSTEM MAXIMUM CURRENT PROTECTION
    Publication number: 20170038815
    Abstract: A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit.
    Type: Application
    Filed: October 21, 2016
    Publication date: February 9, 2017
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Nadav Shulman, Gal Leibovich, Tomer Ziv, Amit Gabai, Jorge P. Rodriguez, Jeffrey A. Carlson
  • Dynamically Controlling Cache Size To Maximize Energy Efficiency
    Publication number: 20170010656
    Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
    Type: Application
    Filed: September 20, 2016
    Publication date: January 12, 2017
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nadav Shulman, Alon Naveh, Hisham Abu-Salah
  • Apparatus and method to track device usage
    Patent number: 9535812
    Abstract: In an embodiment, a processor includes measurement logic to measure a usage associated with the processor. The processor also includes statistical logic to determine, based on a statistical procedure, whether to provide a permission to record an increase in usage responsive to an indication that the usage has increased by a defined amount. The processor also includes control logic to record the defined increase in usage in non-volatile memory responsive to receipt of the permission to record from the statistical logic. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: January 3, 2017
    Assignee: Intel Corporation
    Inventors: Doron Rajwan, Nadav Shulman, Dorit Shapira, Kosta Luria, Efraim Rotem
  • CONTROLLING PERFORMANCE STATES OF PROCESSING ENGINES OF A PROCESSOR
    Publication number: 20160349828
    Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.
    Type: Application
    Filed: May 27, 2015
    Publication date: December 1, 2016
    Inventors: Eliezer Weissmann, Efraim Rotem, Hisham Abu Salah, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Gal Leibovich, Yevgeni Sabin, Shay Levy
  • Power consumption monitoring device for a power source
    Patent number: 9500714
    Abstract: Examples are disclosed for an integrated circuit (IC) device coupled to a battery-operated power supply unit, such as an IC in a mobile computing device or wireless phone, to accurately determine energy usage drawn from the power supply unit under rapidly dynamic circumstances. A current sense signal of a power line from the power supply unit is digitized. The digitized current sense is added to an accumulator at a rate that is approximately proportional to a voltage of the power line from the power supply unit. The accumulator is then outputted and scaled to units relevant to energy measurements. The energy measurement is used to estimate remaining battery life. Triggering the digitization of the current sense signal may be by use of a pulse generation circuit, or by use of an overflow indicator of an accumulator for a digitized voltage sense signal.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: November 22, 2016
    Assignee: INTEL CORPORATION
    Inventors: Efraim Rotem, Nir Rosenzweig, Jeffrey A. Carlson, Philip R. Lehwalder, Nadav Shulman, Doron Rajwan
  • Enabling A Non-Core Domain To Control Memory Bandwidth
    Publication number: 20160313778
    Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.
    Type: Application
    Filed: April 26, 2016
    Publication date: October 27, 2016
    Inventors: Avinash N. Ananthakrishnan, Inder M. Sodhi, Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Ryan Wells
  • System maximum current protection
    Patent number: 9477243
    Abstract: A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: October 25, 2016
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Nadav Shulman, Gal Leibovich, Tomer Ziv, Amit Gabai, Jorge P. Rodriguez, Jeffrey A. Carlson
  • Dynamically controlling cache size to maximize energy efficiency
    Patent number: 9471490
    Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: October 18, 2016
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nadav Shulman, Alon Naveh, Hisham Abu-Salah
  • Controlling Operating Voltage Of A Processor
    Publication number: 20160259389
    Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.
    Type: Application
    Filed: May 18, 2016
    Publication date: September 8, 2016
    Inventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
  • Method, apparatus, and system for energy efficiency and energy conservation including autonomous hardware-based deep power down in devices
    Patent number: 9400545
    Abstract: Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: July 26, 2016
    Assignee: Intel Corporation
    Inventors: Inder M. Sodhi, Alon Naveh, Doron Rajwan, Ryan D. Wells, Eric C. Samson
  • SYSTEM MAXIMUM CURRENT PROTECTION
    Publication number: 20160179110
    Abstract: A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit.
    Type: Application
    Filed: December 22, 2014
    Publication date: June 23, 2016
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Nadav Shulman, Gal Leibovich, Tomer Ziv, Amit Gabai, Jorge P. Rodriguez, Jeffrey A. Carlson
  • Controlling operating voltage of a processor
    Patent number: 9367114
    Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: June 14, 2016
    Assignee: Intel Corporation
    Inventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
  • Enabling a non-core domain to control memory bandwidth in a processor
    Patent number: 9354692
    Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: May 31, 2016
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Inder M. Sodhi, Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Ryan Wells
  • Controlling a turbo mode frequency of a processor
    Patent number: 9292068
    Abstract: In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: March 22, 2016
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Ryan Wells, Nadav Shulman
  • OPTIMIZATION OF ENERGY USAGE IN A PROCESSOR
    Publication number: 20160077569
    Abstract: In an embodiment, a processor includes at least one core and energy performance gain (EPG) logic to determine an EPG frequency based on a first value of an EPG. The EPG is based upon energy consumed by the processor and upon performance of the processor. The processor also includes a clock generator to generate a frequency of operation of the at least one core based on the EPG frequency. Other embodiments are described and claimed.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 17, 2016
    Inventors: Yoni Aizik, Eliezer Weissmann, Efraim Rotem, Yevgeni Sabin, Doron Rajwan, Ahmad Yasin