Patents by Inventor Doron Schupper
Doron Schupper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220360647Abstract: At least a packet header of a packet received by a network device is provided to a programmable header alteration engine that includes a hardware input processor implemented in hardware and a programmable header alteration processor configured to execute computer readable instructions stored in a program memory. The hardware input processor determines whether the packet header is to be provided to a processing path coupled to the programmable header alteration processor or to be diverted to a bypass path that bypasses the programmable header alteration processor, and the packet header is provided to the processing path or to the bypass path based on the determination. The packet header is selectively i) processed by the programmable header alteration processor when the packet header is provided to the processing path and ii) not processed by the programmable header alteration processor when the packet header is provided to the bypass path.Type: ApplicationFiled: May 23, 2022Publication date: November 10, 2022Inventors: Yuval PELED, Doron SCHUPPER, Ilan YERUSHALMI, Rami ZEMACH
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Patent number: 11343358Abstract: At least a packet header of a packet received by a network device is provided to a programmable header alteration engine that includes a hardware input processor implemented in hardware and a programmable header alteration processor configured to execute computer readable instructions stored in a program memory. The hardware input processor determines whether the packet header is to be provided to a processing path coupled to the programmable header alteration processor or to be diverted to a bypass path that bypasses the programmable header alteration processor, and the packet header is provided to the processing path or to the bypass path based on the determination. The packet header is selectively i) processed by the programmable header alteration processor when the packet header is provided to the processing path and ii) not processed by the programmable header alteration processor when the packet header is provided to the bypass path.Type: GrantFiled: January 27, 2020Date of Patent: May 24, 2022Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Yuval Peled, Doron Schupper, Ilan Yerushalmi, Rami Zemach
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Publication number: 20200244780Abstract: At least a packet header of a packet received by a network device is provided to a programmable header alteration engine that includes a hardware input processor implemented in hardware and a programmable header alteration processor configured to execute computer readable instructions stored in a program memory. The hardware input processor determines whether the packet header is to be provided to a processing path coupled to the programmable header alteration processor or to be diverted to a bypass path that bypasses the programmable header alteration processor, and the packet header is provided to the processing path or to the bypass path based on the determination. The packet header is selectively i) processed by the programmable header alteration processor when the packet header is provided to the processing path and ii) not processed by the programmable header alteration processor when the packet header is provided to the bypass path.Type: ApplicationFiled: January 27, 2020Publication date: July 30, 2020Inventors: Yuval PELED, Doron SCHUPPER, Ilan YERUSHALMI, Rami ZEMACH
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Patent number: 9934035Abstract: A data processing device for executing a program is described. The program comprises one or more instruction groups and one or more predicates, each instruction group comprising one or more instructions. The data processing device comprises a processing unit and a trace unit connected to or integrated in the processing unit. The trace unit generates a predicate trace for tracing the values of the one or more predicates. The processing unit executes, in each of a series of execution periods, one of the instruction groups and updated the values of none, one, or more of the predicates in dependence on the respective instruction group. The trace unit appends the updated values of the none, one, or more predicates to the predicate trace and does not append any non-updated values of the predicates. A method of reporting predicate values and a data carrier are also disclosed.Type: GrantFiled: March 21, 2013Date of Patent: April 3, 2018Assignee: NXP USA, Inc.Inventors: Uri Dayan, Erez Arbel-Meirovich, Liron Artsi, Doron Schupper
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Circuitry for a computing system, LSU arrangement and memory arrangement as well as computing system
Patent number: 9436624Abstract: A circuitry for a computing system comprising a first load/store unit, LSU, and a second LSU as well as a memory arrangement. The first LSU is connected to the memory arrangement via a first bus arrangement comprising a first write bus and a first read bus. The second LSU is connected to the memory arrangement via a second bus arrangement comprising a second write bus and a second read bus. The computing system is arranged to carry out a multiple load instruction to read data via the first read bus and the second read bus and/or to carry out a multiple store instruction to write data via the first write bus and the second write bus.Type: GrantFiled: July 26, 2013Date of Patent: September 6, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Ziv Zamsky, Moshe Anschel, Itay Keidar, Itay S. Peled, Doron Schupper, Yakov Tokar -
Publication number: 20160196140Abstract: A data processing device for executing a program is described. The program comprises one or more instruction groups and one or more predicates, each instruction group comprising one or more instructions. The data processing device comprises a processing unit and a trace unit connected to or integrated in the processing unit. The trace unit generates a predicate trace for tracing the values of the one or more predicates. The processing unit executes, in each of a series of execution periods, one of the instruction groups and updated the values of none, one, or more of the predicates in dependence on the respective instruction group. The trace unit appends the updated values of the none, one, or more predicates to the predicate trace and does not append any non-updated values of the predicates. A method of reporting predicate values and a data carrier are also disclosed.Type: ApplicationFiled: March 21, 2013Publication date: July 7, 2016Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Uri DAYAN, Erez ARBEL-MEIR-OVICH, Liron ARTSI, Doron SCHUPPER
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CIRCUITRY FOR A COMPUTING SYSTEM, LSU ARRANGEMENT AND MEMORY ARRANGEMENT AS WELL AS COMPUTING SYSTEM
Publication number: 20150032929Abstract: A circuitry for a computing system comprising a first load/store unit, LSU, and a second LSU as well as a memory arrangement. The first LSU is connected to the memory arrangement via a first bus arrangement comprising a first write bus and a first read bus. The second LSU is connected to the memory arrangement via a second bus arrangement comprising a second write bus and a second read bus. The computing system is arranged to carry out a multiple load instruction to read data via the first read bus and the second read bus and/or to carry out a multiple store instruction to write data via the first write bus and the second write bus.Type: ApplicationFiled: July 26, 2013Publication date: January 29, 2015Inventors: ZIV ZAMSKY, MOSHE ANSCHEL, ITAY KEIDAR, ITAY S. PELED, DORON SCHUPPER, YAKOV TOKAR -
Publication number: 20140019990Abstract: An integrated circuit device comprising an instruction processing module for performing operations on data in accordance with received instructions. The instruction processing module comprises a context selector unit arranged to selectively provide access to at least one process attribute(s) within a plurality of process contexts in accordance with at least one context selector value received thereby. The instruction processing module is arranged to receive an instruction comprising a context indication for a process attribute with which an operation is to be performed, provide the context selector value based at least partly on the context indication to the context selector unit, and execute the operation to be performed with the process attribute for at least one process context to which the context selector unit provides access in accordance with the context selector value.Type: ApplicationFiled: March 30, 2011Publication date: January 16, 2014Applicant: Freescale Semiconductor, Inc.Inventors: Doron Schupper, Itzhak Barak, Uri Dayan, Noam Eshel-Goldman, Lev Vaskevich
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Publication number: 20130326200Abstract: An integrated circuit device comprising at least one instruction processing module arranged to compare validation data with data stored within a target register upon receipt of a load validation instruction. Wherein, the instruction processing module is further arranged to proceed with execution of a next sequential instruction if the validation data matches the stored data within the target register, and to load the validation data into the target register if the validation data does not match the stored data within the target register.Type: ApplicationFiled: February 11, 2011Publication date: December 5, 2013Applicant: Freescale Semiconductor, Inc.Inventors: Amir Kleen, Itzhak Barak, Yuval Peled, Idan Rozenberg, Doron Schupper
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Publication number: 20130290686Abstract: An integrated circuit device comprises at least one instruction processing module arranged to perform branch predication. The at least one instruction processing module comprises at least one predicate calculation module arranged to receive as an input at least one result vector for a predicate function and at least one conditional parameter value therefor and output a predicate result value from the at least one result vector based at least partly on the at least one received conditional parameter value.Type: ApplicationFiled: January 21, 2011Publication date: October 31, 2013Applicant: Freescale Semiconductor, Inc.Inventors: Yuval Peled, Itzhak Barak, Idan Rozenberg, Doron Schupper, Lev Vaskevich
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Method for executing an instruction loop and a device having instruction loop execution capabilities
Patent number: 8266414Abstract: A method for managing a hardware instruction loop, the method includes: (i) detecting, by a branch prediction unit, an instruction loop; wherein a size of the instruction loop exceeds a size of a storage space allocated in a fetch unit for storing fetched instructions; (ii) requesting from the fetch unit to fetch instructions of the instruction loop that follow the first instructions of the instruction loop; and (iii) selecting, during iterations of the instruction loop, whether to provide to a dispatch unit one of the first instructions of the instruction loop or another instruction that is fetched by the fetch unit; wherein the first instructions of the instruction loop are stored at the dispatch unit.Type: GrantFiled: August 19, 2008Date of Patent: September 11, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Lev Vaskevich, Itzhak Barak, Amir Paran, Yuval Peled, Idan Rozenberg, Doron Schupper -
Patent number: 7930522Abstract: A method for speculative execution of instructions, the method includes: decoding a compare instruction; speculatively executing, in a continuous manner, conditional instructions that are conditioned by a condition that is related to a resolution of the compare instruction and are decoded during a speculation window that starts at the decoding of the compare instruction and ends when the compare instruction is resolved; and stalling an execution of a non-conditional instruction that is dependent upon an outcome of at least one of the conditional instructions, until the speculation window ends.Type: GrantFiled: August 19, 2008Date of Patent: April 19, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Guy Shumeli, Itzhak Barak, Uri Dayan, Amir Paran, Idan Rozenberg, Doron Schupper
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Publication number: 20100049958Abstract: A method for managing a hardware instruction loop, the method includes: (i) detecting, by a branch prediction unit, an instruction loop; wherein a size of the instruction loop exceeds a size of a storage space allocated in a fetch unit for storing fetched instructions; (ii) requesting from the fetch unit to fetch instructions of the instruction loop that follow the first instructions of the instruction loop; and (iii) selecting, during iterations of the instruction loop, whether to provide to a dispatch unit one of the first instructions of the instruction loop or another instruction that is fetched by the fetch unit; wherein the first instructions of the instruction loop are stored at the dispatch unit.Type: ApplicationFiled: August 19, 2008Publication date: February 25, 2010Inventors: Lev Vaskevich, Itzhak Barak, Amir Paran, Yuval Peled, Idan Rozenberg, Doron Schupper
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Publication number: 20100049954Abstract: A method for speculative execution of instructions, the method includes: decoding a compare instruction; speculatively executing, in a continuous manner, conditional instructions that are conditioned by a condition that is related to a resolution of the compare instruction and are decoded during a speculation window that starts at the decoding of the compare instruction and ends when the compare instruction is resolved; and stalling an execution of a non-conditional instruction that is dependent upon an outcome of at least one of the conditional instructions, until the speculation window ends.Type: ApplicationFiled: August 19, 2008Publication date: February 25, 2010Inventors: Guy Shmueli, Itzhak Barak, Uri Dayan, Amir Paran, Idan Rozenberg, Doron Schupper
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Publication number: 20050246498Abstract: Read/write conflicts in an instruction cache memory (11) are reduced by configuring the memory as two even and odd array sub-blocks (12,13) and adding an input buffer (10) between the memory (11) and an update (16). Contentions between a memory read and a memory write are minimised by the buffer (10) shifting the update sequence with respect to the read sequence. The invention can adapt itself for use in digital signal processing systems with different external memory behaviour as far as latency and burst capability is concerned.Type: ApplicationFiled: March 3, 2003Publication date: November 3, 2005Inventors: Doron Schupper, Yakov Tokar, Jacob Efrat
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Patent number: 6848030Abstract: A processing system has a processor, a cache, and a fetch unit. If there is a miss in the cache, the fetch unit generates a fetch address for the miss in the cache for the purpose of retrieving the requested data from external memory and providing the data to the processor and loading the data in a location in a line in the cache. The fetch unit also generates additional prefetch addresses for addresses consecutive with the fetch address. The prefetch addresses continue to be generated for all of the locations in the line in the cache that are consecutive with the fetch address. The generation of prefetch addresses will be stopped if another requests arrives that is not part of the already generated prefetched addresses. Further, the outstanding prefetches will be terminated if the external memory can handle such termination.Type: GrantFiled: July 20, 2001Date of Patent: January 25, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Yakov Tokar, Amit Gur, Jacob Efrat, Doron Schupper
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Publication number: 20030041213Abstract: A cache is used in the performance of one task that may be interrupted by another task. The first task results in the cache being loaded at least partially. The second task interrupts, but is preventing from thrashing the highest priority data. The highest priority data is not available for thrashing during the running of the second task. The second task may be interrupted as well. Similarly, the third task is prevented from thrashing the highest priority data of the second task and the first task. The third task can thrash all of the cache except that preserved for the first and second tasks. After the third task is completed, the second task can begin running again without having to reload the highest priority data. The first task is similarly completed.Type: ApplicationFiled: August 24, 2001Publication date: February 27, 2003Inventors: Yakov Tokar, Yacov Efrat, Doron Schupper, Brett L. Lindsley
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Publication number: 20030018853Abstract: A processing system has a processor, a cache, and a fetch unit. If there is a miss in the cache, the fetch unit generates a fetch address for the miss in the cache for the purpose of retrieving the requested data from external memory and providing the data to the processor and loading the data in a location in a line in the cache. The fetch unit also generates additional prefetch addresses for addresses consecutive with the fetch address. The prefetch addresses continue to be generated for all of the locations in the line in the cache that are consecutive with the fetch address. The generation of prefetch addresses will be stopped if another requests arrives that is not part of the already generated prefetched addresses. Further, the outstanding prefetches will be terminated if the external memory can handle such termination.Type: ApplicationFiled: July 20, 2001Publication date: January 23, 2003Inventors: Yakov Tokar, Amit Gur, Jacob Efrat, Doron Schupper