Patents by Inventor Doron Shamia

Doron Shamia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7930566
    Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: April 19, 2011
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Avi (Abraham) Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
  • Publication number: 20110072164
    Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
    Type: Application
    Filed: September 16, 2010
    Publication date: March 24, 2011
    Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Avi (Abraham) Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
  • Patent number: 7899943
    Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: March 1, 2011
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Avi (Arraham) Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
  • Patent number: 7900031
    Abstract: A multiple, cooperating operating systems (OS) platform system with multi processors. Multiple operating systems, each of which may be of a different type or nature, can run on different partitions of the multi-processor platform and yet coexist and cooperate. A real time operating system (RTOS) executing on a processor can communicate with another OS executing on another processor via a portion of memory accessible by the RTOS and the OS by perform read and write operations.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: March 1, 2011
    Assignee: Intel Corporation
    Inventors: Doron Shamia, Ron Gabor, Yoram Kullbak, Randolph L. Campbell, Jimmy Scott Raynor, Tiags Thiyagarajah
  • Publication number: 20100333077
    Abstract: The present invention generally relates to a method for describing network events in a service aware network (“SAN”). In addition, the present invention relates to software that performs the method and has a programming model containing protocol libraries, abstract protocol messages declarations, and network events. The method and software enable a user to define basic as well as complex network events in the application, presentation, session, transport and/or network layers of a communication model, which result in internet protocol (“IP”) level triggers or other triggers. Such triggers will result in actions which may be applicable in all layers of a communication model up to the highest layer. As a result, the method and software allow a user to describe a hierarchy of high level network events through a hierarchy of lower level events. In addition, a development system and an apparatus which utilizes the method and software are also provided.
    Type: Application
    Filed: April 5, 2010
    Publication date: December 30, 2010
    Inventors: Yuval Shachar, Doron Shamia, Oren Ravoy
  • Patent number: 7844688
    Abstract: The present invention generally relates to a method for describing network events in a service aware network (“SAN”). In addition, the present invention relates to software that performs the method and has a programming model containing protocol libraries, abstract protocol messages declarations, and network events. The method and software enable a user to define basic as well as complex network events in the application, presentation, session, transport and/or network layers of a communication model, which result in internet protocol (“IP”) level triggers or other triggers. Such triggers will result in actions which may be applicable in all layers of a communication model up to the highest layer. As a result, the method and software allow a user to describe a hierarchy of high level network events through a hierarchy of lower level events. In addition, a development system and an apparatus which utilizes the method and software are also provided.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: November 30, 2010
    Assignee: P-Cube Ltd.
    Inventors: Doron Shamia, Yuval Shachar, Oren Ravoy
  • Patent number: 7827551
    Abstract: An embodiment of the present invention is a technique to provide a real-time threading service to an application in a multi-core environment. An executive is launched, within a most privilege level of an operating system (OS), on a real-time core in the multi-core environment. The real-time core is sequestered from the OS. A real-time thread is created in a least privilege level on the real-time core for an application using a library. The library is loaded by the application. The real-time thread shares a virtual address space with the application.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: November 2, 2010
    Assignee: Intel Corporation
    Inventors: Yoram Kulbak, Doron Shamia, Jimmy Scott Raynor, James P. Held, Ron Gabor
  • Publication number: 20090064178
    Abstract: A multiple, cooperating operating systems (OS) platform system with multi processors. Multiple operating systems, each of which may be of a different type or nature, can run on different partitions of the multi-processor platform and yet coexist and cooperate. A real time operating system (RTOS) executing on a processor can communicate with another OS executing on another processor via a portion of memory accessible by the RTOS and the OS by perform read and write operations.
    Type: Application
    Filed: August 28, 2008
    Publication date: March 5, 2009
    Inventors: Doron Shamia, Yoram Kulbak, Ron Gabor, Randolph L. Campbell, Jimmy Scott Raynor, Tiags Thiyagarajah
  • Patent number: 7437546
    Abstract: Embodiments of a multi-processor platform including multiple, cooperating operating systems are described. Multiple operating systems, each of which may be of a different type or nature, run on different partitions of the multi-processor platform, yet coexist and cooperate. In various embodiments, different specialized operating systems, suitable for particular tasks, run on different partitions of the platform. In one embodiment, a host operating system, using a driver, boots and partitions a portion of the platform running other operating systems, and then communicates with, and shares work with, the other operating systems. In one embodiment, the multi-processor platform includes a host operating system and multiple specialized operating systems, such as real-time operating systems, operating alongside the host operating system. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: October 14, 2008
    Assignee: Intel Corporation
    Inventors: Doron Shamia, Yoram Kulbak, Ron Gabor, Randolph L. Campbell, Jimmy S. Raynor, Tiags Thiyagarajah
  • Publication number: 20080215822
    Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
    Type: Application
    Filed: October 31, 2007
    Publication date: September 4, 2008
    Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Avi (Abraham) Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
  • Publication number: 20080195791
    Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
    Type: Application
    Filed: October 31, 2007
    Publication date: August 14, 2008
    Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dian Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Avi (Abraham) Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
  • Publication number: 20080196034
    Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
    Type: Application
    Filed: October 31, 2007
    Publication date: August 14, 2008
    Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanaliur, James Akiyama, Robert Blankenship, Ohad Falik, Avi (Arraham) Mendelson, Ilan Pardo, Eran Tamari, Ellezer Weissmann, Doron Shamia
  • Publication number: 20080195780
    Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
    Type: Application
    Filed: October 31, 2007
    Publication date: August 14, 2008
    Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Avi (Arraham) Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
  • Publication number: 20080109565
    Abstract: A method and apparatus for enhancing /extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
    Type: Application
    Filed: November 2, 2006
    Publication date: May 8, 2008
    Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Fallk, Avi Arraham Mendelson, Ilan Pardo, Eran Tamari, Ellezer Weissmann, Doron Shamia
  • Publication number: 20070067771
    Abstract: An embodiment of the present invention is a technique to provide a real-time threading service to an application in a multi-core environment. An executive is launched, within a most privilege level of an operating system (OS), on a real-time core in the multi-core environment. The real-time core is sequestered from the OS. A real-time thread is created in a least privilege level on the real-time core for an application using a library. The library is loaded by the application. The real-time thread shares a virtual address space with the application.
    Type: Application
    Filed: September 21, 2005
    Publication date: March 22, 2007
    Inventors: Yoram Kulbak, Doron Shamia, Jimmy Raynor, James Held, Ron Gabor
  • Publication number: 20070033389
    Abstract: Embodiments of a multi-processor platform including multiple, cooperating operating systems are described. Multiple operating systems, each of which may be of a different type or nature, run on different partitions of the multi-processor platform, yet coexist and cooperate. In various embodiments, different specialized operating systems, suitable for particular tasks, run on different partitions of the platform. In one embodiment, a host operating system, using a driver, boots and partitions a portion of the platform running other operating systems, and then communicates with, and shares work with, the other operating systems. In one embodiment, the multi-processor platform includes a host operating system and multiple specialized operating systems, such as real-time operating systems, operating alongside the host operating system. Other embodiments are described and claimed.
    Type: Application
    Filed: August 3, 2005
    Publication date: February 8, 2007
    Inventors: Doron Shamia, Yoram Kulbak, Ron Gabor, Randolph Campbell, Jimmy Raynor, Tiags Thiyagarajah
  • Publication number: 20060195556
    Abstract: The present invention generally relates to a method for describing network events in a service aware network (“SAN”). In addition, the present invention relates to software that performs the method and has a programming model containing protocol libraries, abstract protocol messages declarations, and network events. The method and software enable a user to define basic as well as complex network events in the application, presentation, session, transport and/or network layers of a communication model, which result in internet protocol (“IP”) level triggers or other triggers. Such triggers will result in actions which may be applicable in all layers of a communication model up to the highest layer. As a result, the method and software allow a user to describe a hierarchy of high level network events through a hierarchy of lower level events. In addition, a development system and an apparatus which utilizes the method and software are also provided.
    Type: Application
    Filed: January 3, 2006
    Publication date: August 31, 2006
    Inventors: Doron Shamia, Yuval Shachar, Oren Ravoy
  • Publication number: 20030126234
    Abstract: The present invention generally relates to a method for describing network events in a service aware network (“SAN”). In addition, the present invention relates to software that performs the method and has a programming model containing protocol libraries, abstract protocol messages declarations, and network events. The method and software enable a user to define basic as well as complex network events in the application, presentation, session, transport and/or network layers of a communication model, which result in internet protocol (“IP”) level triggers or other triggers. Such triggers will result in actions which may be applicable in all layers of a communication model up to the highest layer. As a result, the method and software allow a user to describe a hierarchy of high level network events through a hierarchy of lower level events. In addition, a development system and an apparatus which utilizes the method and software are also provided.
    Type: Application
    Filed: November 20, 2001
    Publication date: July 3, 2003
    Applicant: P-CUBE LTD.
    Inventors: Yuval Shachar, Doron Shamia, Oren Ravoy