Abstract: A method comprising receiving, by a one-time pad (OTP) hub, from a first user of a computer network, a communication encrypted with an OTP associated with said first user, wherein said communication is intended for a second user; encrypting, by said hub, said communication with an OTP associated with said second user; decrypting, by said hub, said communication with an OTP associated with said first user; and delivering said communication to said second user.

Abstract: A method and a wearable system which includes distance sensors, cameras and headsets, which all gather data about a blind or visually impaired person's surroundings and are all connected to a portable personal communication device, the device being configured to use scenario-based algorithms and an A.I to process the data and transmit sound instructions to the blind or visually impaired person to enable him/her to independently navigate and deal with his/her environment by provision of identification of objects and reading of local texts.

Abstract: A method comprising receiving, by a one-time pad (OTP) hub, from a first user of a computer network, a communication encrypted with an OTP associated with said first user, wherein said communication is intended for a second user; encrypting, by said hub, said communication with an OTP associated with said second user; decrypting, by said hub, said communication with an OTP associated with said first user; and delivering said communication to said second user.

Abstract: A system comprising: at least one hardware processor; and a non-transitory computer-readable storage medium having stored thereon program instructions, the program instructions executable by the at least one hardware processor to: receive, by a routing hub in a computer network, from an origin node, a communication intended to a destination node, wherein said communication is encrypted with a one-time pad (OTP) associated with said origin node, apply, by said routing hub, to said communication, a customized OTP configured to simultaneously (i) encrypt said communication with said OTP associated with said destination node, and (ii) decrypt said communication with said OTP associated with said origin node, and deliver said communication to said destination node for decrypting said communication with said OTP associated with said destination node.

Abstract: A method comprising receiving, by a one-time pad (OTP) hub, from a first user of a computer network, a communication encrypted with an OTP associated with said first user, wherein said communication is intended for a second user; encrypting, by said hub, said communication with an OTP associated with said second user; decrypting, by said hub, said communication with an OTP associated with said first user; and delivering said communication to said second user.

Abstract: A method and a wearable system which includes distance sensors, cameras and headsets, which all gather data about a blind or visually impaired person's surroundings and are all connected to a portable personal communication device, the device being configured to use scenario-based algorithms and an A.I to process the data and transmit sound instructions to the blind or visually impaired person to enable him/her to independently navigate and deal with his/her environment by provision of identification of objects and reading of local texts.

Abstract: A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms is disclosed. The chip architecture comprises a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols. Preferably, at least some of the same megafunctions are used with algorithms of two or more protocols.

Abstract: A chip architectural core is described for use in decoding one or more vectors received by the core in accordance with one or more recursive and/or non-recursive systematic trellis codes of varying sizes and constraints K, as well as generator polynomials. The core comprises: a decoder including (a) a reconfigurable network of ACS blocks, BMU generators and trace-back mechanisms for both recursive and non-recursive systematic forms, and (b) reconfigurable connections between the ACS blocks, BMU generators and trace-back mechanisms, arranged so that the precise number of network components can be continuously rearranged and interconnected in a network as a function of size and the constraint K and generator polynomial of each code used for encoding the vectors received by the core.

Abstract: A reconfigurable architecture for and method of performing a fast orthogonal transform of vectors in multiple stages, the size of a vector being N, wherein N can vary and the number of stages is a function of N, the architecture comprising: a computational unit configured and arranged so as to include one or more butterfly units; a block including one or more multipliers coupled to the output of the computational unit, configured and arranged so as to perform all of the butterfly computations for at least one stage of the transform; a storage unit configured and arranged so as to store the intermediate results of the butterfly computations and predetermined coefficients for use by the computational unit for performing each butterfly computation, the storage unit including memory and multiplexing architecture; the storage unit including memory and multiplexing architecture; a multiplexer unit configured and arranged so as to time multiplex all of the butterfly computations of the transform using said comput

Abstract: An integrated chip for use in processing signals encoded in accordance with either one of at least two communication protocols comprises: reconfigurable architecture capable of being selectively arranged into different configurations, at least one configuration corresponding to each respective protocol so as to implement the functionality of the respective protocol with a predetermined complexity, and an intermediate configuration for implementing the hand-off between a first protocol and a second protocol. The intermediate configuration is arranged so as to simultaneously implement the basic functionality of both the first and second protocols during hand-off, and implementation of at least one of the protocols is of lesser complexity than of the corresponding predetermined complexity associated with separately implementing the other of the protocols.

Abstract: A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms is disclosed. The chip architecture comprises a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols. Preferably, at least some of the same megafunctions are used with algorithms of two or more protocols.

Abstract: An apparatus and method for control in a reconfigurable architecture is shown and described. In one example, an integrated circuit configured to implement a plurality of communications standards includes a plurality of upper level controllers and a plurality of lower level controllers. The upper level controller are configured to operate according to a portion of a communications standard and implement upper level control functions for the associated standard. The low level controllers are capable of communicating with each of the upper level controllers and can be assigned to each of the upper level controls to implement low level functions of each of the plurality of communications standards.

Abstract: A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms is disclosed. The chip architecture comprises a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols. Preferably, at least some of the same megafunctions are used with algorithms of two or more protocols.

Abstract: A chip architectural core is described for use in decoding one or more vectors received by the core in accordance with one or more recursive and/or non-recursive systematic trellis codes of varying sizes and constraints K, as well as generator polynomials. The core comprises: a decoder including (a) a reconfigurable network of ACS blocks, BMU generators and trace-back mechanisms for both recursive and non-recursive systematic forms, and (b) reconfigurable connections between the ACS blocks, BMU generators and trace-back mechanisms, arranged so that the precise number of network components can be continuously rearranged and interconnected in a network as a function of size and the constraint K and generator polynomial of each code used for encoding the vectors received by the core.

Abstract: A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms is disclosed. The chip architecture comprises a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols. Preferably, at least some of the same megafunctions are used with algorithms of two or more protocols.

Abstract: A reconfigurable architecture for and method of performing a fast orthogonal transform of vectors in multiple stages, the size of a vector being N, wherein N can vary and the number of stages is a function of N, the architecture comprising: a computational unit configured and arranged so as to include one or more butterfly units; a block including one or more multipliers coupled to the output of the computational unit, configured and arranged so as to perform all of the butterfly computations for at least one stage of the transform; a storage unit configured and arranged so as to store the intermediate results of the butterfly computations and predetermined coefficients for use by the computational unit for performing each butterfly computation, the storage unit including memory and multiplexing architecture; the storage unit including memory and multiplexing architecture; a multiplexer unit configured and arranged so as to time multiplex all of the butterfly computations of the transform using said computati