Abstract: A mechanism provides for sending an envelope and replying to an envelope. A transmitter is configured to send an envelope. A receiver is coupled to the transmitter, wherein the receiver is configured to receive the envelope and generate a reply envelope. A send buffer is coupled to the transmitter. A receive buffer is coupled to the receiver. A retry timer is coupled to the transmitter, wherein the retry timer is configured to reset upon the receipt of a reply envelope correlated to the transmit envelope. The transmitter is configured to retransmit an envelope if the transmitter does not receive a corresponding reply envelope within a selected time period as determined by the retry timer. This leads to a decrease in the total number of envelopes, transmitted from both the transmitter and the receiver.

Abstract: Techniques for validating the integrity of a data communications link are provided. By executing error correction/detection calculations, such as CRC calculations, in a pipelined manner, logic may be distributed over multiple machine cycles. As a result, delay involved in the logic for each cycle may be reduced, allowing calculations in systems with higher clock frequencies.

Abstract: A method and apparatus are provided for implementing bandwidth control in a communication link. A set link configuration for the communications link establishes a number of clock cycles required to transmit a data envelope. A control function aligns a start of a data packet on a fixed cycle boundary for data envelope transmissions. The control function aligns the start of a data packet in the same byte of the 16 byte field. The control function is implemented with a memory management input/output (MMIO) register and a counter, and allows a transmitting side of the communications link to control the pacing of data packet transmission or bandwidth by aligning all data packets on fixed-cycle boundaries.

Abstract: A method and apparatus are provided for managing dependencies between split command and data transactions. A command transaction is written into a command array. A data transaction is written into a data array. A marker is defined for both command transactions and data transactions, and a marked command counter is maintained. Marked data will not be sent unless the older commands have been sent. A data header is marked if the previous transaction written was a command, and a command is marked if the previous transaction written was data. The marked command counter maintains a count of marked commands sent relative to sending marked data.

Abstract: Techniques for validating the integrity of a data communications link are provided. By executing error correction/detection calculations, such as CRC calculations, in a pipelined manner, logic may be distributed over multiple machine cycles.

Abstract: In a first aspect, a first method of controlling a non-functional operation on a memory of a computer system using software is provided. The first method includes the steps of (1) employing a processor to write bits of data to at least one register external to the processor, wherein the bits of data serve as control bits for the memory; and (2) applying the bits of data to respective pins of the memory so as to cause the non-functional operation to be performed on the memory. Numerous other aspects are provided.

Abstract: In a first aspect, a first method of testing a link between a first chip and a second chip is provided. The first method includes the steps of, while operating in a test mode, (1) transmitting test data of sufficient length to enable exercising of worst case transitions from the first chip to the second chip via the link; and (2) performing cyclic redundancy checking (CRC) on the test data to test the link. Numerous other aspects are provided.

Abstract: In a first aspect, a first method of testing a link between a first chip and a second chip is provided. The first method includes the steps of, while operating in a test mode, (1) transmitting test data of sufficient length to enable exercising of worst case transitions from the first chip to the second chip via the link; and (2) performing cyclic redundancy checking (CRC) on the test data to test the link. Numerous other aspects are provided.

Abstract: A method and apparatus are provided for managing dependencies between split command and data transactions. A command transaction is written into a command array. A data transaction is written into a data array. A marker is defined for both command transactions and data transactions, and a marked command counter is maintained. Marked data will not be sent unless the older commands have been sent. A data header is marked if the previous transaction written was a command, and a command is marked if the previous transaction written was data. The marked command counter maintains a count of marked commands sent relative to sending marked data.