Patents by Inventor Dosi Dosev
Dosi Dosev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11649158Abstract: A microelectromechanical systems (MEMS) device includes a MEMS device body connected to a first mooring portion and a second mooring portion. The MEMS device body further includes a first cantilever and a second cantilever and connected by a spring. The spring is in operable communication with the first cantilever and the second cantilever.Type: GrantFiled: July 22, 2019Date of Patent: May 16, 2023Assignee: Rosemount Aerospace Inc.Inventors: Dosi Dosev, David P. Potasek, Marcus Allen Childress
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Patent number: 11245006Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.Type: GrantFiled: December 23, 2019Date of Patent: February 8, 2022Assignees: Polar Semiconductor, LLC, SANKEN ELECTRIC CO., LTD.Inventors: Dosi Dosev, Don Rankila, Tatsuya Kamimura, Shunsuke Fukunaga, Steven L. Kosier, Peter West
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Publication number: 20210024350Abstract: A MEMS device includes a first layer, a second layer connected to the first layer, a first mooring portion, a second mooring portion, and a MEMS device body. The MEMS device body is connected to the first mooring portion and the second mooring portion. The MEMS device body further includes a first cantilever attached to the first mooring portion, a second cantilever attached to the second mooring portion, and a spring. The spring is in operable communication with the first cantilever and the second cantilever.Type: ApplicationFiled: July 22, 2019Publication date: January 28, 2021Inventors: Dosi Dosev, David P. Potasek, Marcus Allen Childress
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Patent number: 10896885Abstract: Apparatus and associated methods relate to a bond-pad structure having small pad-substrate capacitance for use in high-voltage MOSFETs. The bond-pad structure includes upper and lower polysilicon plates interposed between a metal bonding pad and an underlying semiconductor substrate. The lower polysilicon plate is encapsulated in dielectric materials, thereby rendering it floating. The upper polysilicon plate is conductively coupled to a source of the high-voltage MOSFET. A perimeter of the metal bonding pad is substantially circumscribed, as viewed from a plan view perspective, by a perimeter of the upper polysilicon plate. A perimeter of the upper polysilicon plate is substantially circumscribed, as viewed from the plan view perspective, by a perimeter of the lower polysilicon plate. In some embodiments, the metal bonding pad is conductively coupled to a gate of the high-voltage MOSFET. The pad-substrate capacitance is advantageously made small by this bond-pad structure.Type: GrantFiled: September 13, 2017Date of Patent: January 19, 2021Assignees: Polar Semiconductor, LLC, Sanken Electric Co., Ltd.Inventors: Peter West, Dosi Dosev, Don Rankila, Tatsuya Kamimura, Steve Kosier
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Patent number: 10662058Abstract: A method of manufacturing a patterned aluminum nitride layer includes growing an amorphous patterned layer on a seed layer, which promotes growth of a first type aluminum nitride layer that has a disordered crystallographic structure. The seed layer promotes growth of a second type aluminum nitride layer with a vertically oriented columnar crystal structure. The method also includes depositing an aluminum nitride layer over the amorphous patterned layer and the seed layer to form the first type aluminum nitride layer with the disordered crystallographic structure over the amorphous patterned layer and the second type aluminum nitride layer with the vertically oriented columnar crystal structure over the seed layer. The method also includes depositing a masking layer over the second type aluminum nitride layer and etching away the first type aluminum nitride layer.Type: GrantFiled: March 5, 2019Date of Patent: May 26, 2020Assignee: Rosemount Aerospace Inc.Inventor: Dosi Dosev
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Publication number: 20200127092Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.Type: ApplicationFiled: December 23, 2019Publication date: April 23, 2020Applicants: Polar Semiconductor, LLC, SANKEN ELECTRIC CO., LTD.Inventors: Dosi Dosev, Don Rankila, Tatsuya Kamimura, Shunsuke Fukunaga, Steven L. Kosier, Peter West
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Patent number: 10580861Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.Type: GrantFiled: February 20, 2018Date of Patent: March 3, 2020Assignees: POLAR SEMICONDUCTOR, LLC, SANKEN ELECTRIC CO., LTD.Inventors: Dosi Dosev, Don Rankila, Tatsuya Kamimura, Shunsuke Fukunaga, Steven Kosier, Peter West
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Publication number: 20190081016Abstract: Apparatus and associated methods relate to a bond-pad structure having small pad-substrate capacitance for use in high-voltage MOSFETs. The bond-pad structure includes upper and lower polysilicon plates interposed between a metal bonding pad and an underlying semiconductor substrate. The lower polysilicon plate is encapsulated in dielectric materials, thereby rendering it floating. The upper polysilicon plate is conductively coupled to a source of the high-voltage MOSFET. A perimeter of the metal bonding pad is substantially circumscribed, as viewed from a plan view perspective, by a perimeter of the upper polysilicon plate. A perimeter of the upper polysilicon plate is substantially circumscribed, as viewed from the plan view perspective, by a perimeter of the lower polysilicon plate. In some embodiments, the metal bonding pad is conductively coupled to a gate of the high-voltage MOSFET. The pad-substrate capacitance is advantageously made small by this bond-pad structure.Type: ApplicationFiled: September 13, 2017Publication date: March 14, 2019Inventors: Peter West, Dosi Dosev, Don Rankila, Tatsuya Kamimura, Steve Kosier
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Publication number: 20190081147Abstract: Apparatus and associated methods relate to a trench Metal-Oxide-Semiconductor Field-effect Transistor (MOSFET). The trench MOSFET includes a pair of longitudinal trenches formed in a semiconductor die, thereby forming an intervening longitudinal semiconductor pillar therebetween. Each of the pair of trenches has a field plates dielectrically isolated from a conductive gate. Each of the conductive gates is dielectrically isolated from the intervening semiconductor pillar via a gate dielectric. The thickness of the gate dielectric varies along a vertical dimension of the conductive gate, thereby providing a variation in a separation distance between each conductive gate and the intervening semiconductor pillar. The separation distance decreases from a gate/source overlap region to a channel inversion region. Such a varying separation distance can advantageously improve MOSFET operating parameters.Type: ApplicationFiled: September 13, 2017Publication date: March 14, 2019Inventors: Peter West, Dosi Dosev, Don Rankila, Tatsuya Kamimura, Steve Kosier
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Publication number: 20180175146Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.Type: ApplicationFiled: February 20, 2018Publication date: June 21, 2018Inventors: Dosi Dosev, Don Rankila, Tatsuya Kamimura, Shunsuke Fukunaga, Steven Kosier, Peter West
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Publication number: 20160247879Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern including a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.Type: ApplicationFiled: February 23, 2016Publication date: August 25, 2016Inventors: Dosi Dosev, Don Rankila, Tatsuya Kamimura, Shunsuke Fukunaga, Steven Kosier, Peter West
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Publication number: 20110037069Abstract: Etch depth of a material in a semiconductor wafer may be determined by forming a production region and a test region of the wafer, the test region having a test pattern for determining etch depth on a the wafer. The semiconductor wafer is comprised of a base layer, an intermediate layer above and visually distinguishable from the base layer, and a mask of photoresist material formed atop the intermediate layer. The mask of photoresist material has an areal photoresist coverage that varies across a horizontal axis. When the wafer is etched, a visible boundary can be seen between a region where the intermediate layer has been entirely etched away, and a region where at least some of the intermediate layer remains. The horizontal position of this visible boundary corresponds to the vertical etch depth in the production region., after etching of the semiconductor wafer.Type: ApplicationFiled: August 13, 2009Publication date: February 17, 2011Applicant: Polar Semiconductor, Inc.Inventors: Peter West, Dosi Dosev
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Publication number: 20090227044Abstract: A single microchannel is combined with external electromagnets for performing a fast immunoassay within a very small volume. Magnetic/luminescent nanoparticles serve as carriers for the antibodies and as internal luminescent standard. The immunoreaction is accelerated by applying alternating magnetic field by means of the external electromagnets, thus inducing oscillation of the particles and achieving better diffusion during the incubation steps. Using the electromagnets the particles are held into the channel for washing and luminescence detection steps. The luminescence of the particles serves as an internal calibration for the assay and helps to avoid experimental error from particle loss.Type: ApplicationFiled: January 26, 2007Publication date: September 10, 2009Inventors: Dosi Dosev, Vishal Talwar, Mikaela Nichkova, Ian Kennedy