Abstract: A method for performing content-based video compression using reinforcement learning (RL) for video rate control for a downstream task is provided. The method includes processing frame information associated with a raw frame from a video using an RL agent to generate quantization parameter (QP) information that indicates one or more values associated with a compression level of the raw frame and encoding the raw frame into a bitstream based on the QP information. The method further includes reconstructing the raw frame using the bitstream to obtain a reconstructed frame and processing the raw frame as well as the reconstructed frame using a pre-trained downstream model to generate two outputs. The method then includes determining a downstream task reward based on the two outputs and training the RL agent based on the downstream task reward.

Abstract: A method for performing content-based video compression using reinforcement learning (RL) is provided. The method includes obtaining frame information associated with a frame from a video. The frame information comprises quantization parameter (QP) information associated with the frame, and the QP information indicates an initial compression level for encoding aspects of the frame. The frame information and additional information are processed by an RL agent to generate a generated QP map indicating a plurality of updated values associated with a plurality of macro-blocks (MBs) of the frame. A bitstream is generated comprising a plurality of bits for the frame based on the generated QP map. Specifically, the plurality of updated values from the generated QP map indicates an amount of allocated bits from the bitstream to allocate for each of the plurality of MBs. The bitstream is provided to a downstream model.

Abstract: In one embodiment, a syntonization system includes a device including a dedicated clock signal input interface to be connected by a clock connection to a remote device and to receive a remote clock signal from the remote device, the remote device being external to the device, and clock circuitry to generate a local clock signal, and a digital clock controller to generate digital control signals to control the clock circuitry to syntonize the local clock signal according to the remote clock signal based on a difference between frequencies of the remote clock signal and the local clock signal, and provide the digital control signals to the clock circuitry, wherein the clock circuitry is to adjust the frequency of the local clock signal based on the digital control signals.

Abstract: Apparatuses, systems, and associated methods of manufacturing are described that provide a dynamic data interconnect and networking cable configuration. The dynamic data interconnect includes a substrate, transmitters supported on the substrate configured to generate signals, and receivers supported on the substrate configured to receive signals. The dynamic data interconnect further includes a number of connection pads that receive data cables attached thereto and a number of transmission lanes that operably couple the transmitters and receivers to the connection pads. The dynamic data interconnect further includes transmission circuitry in communication with each of the transmitters and receivers such that, in an operational configuration, the transmission circuitry determines a transmission state of the dynamic data interconnect and selectively disables operation of at least a portion of the transmitters or at least a portion of the receivers.

Abstract: Apparatuses, systems, and associated methods of manufacturing are described that provide a dynamic data interconnect and networking cable configuration. The dynamic data interconnect includes a substrate, transmitters supported on the substrate configured to generate signals, and receivers supported on the substrate configured to receive signals. The dynamic data interconnect further includes a number of connection pads that receive data cables attached thereto and a number of transmission lanes that operably couple the transmitters and receivers to the connection pads. The dynamic data interconnect further includes transmission circuitry in communication with each of the transmitters and receivers such that, in an operational configuration, the transmission circuitry determines a transmission state of the dynamic data interconnect and selectively disables operation of at least a portion of the transmitters or at least a portion of the receivers.

Abstract: Described embodiments include a system that includes one or more buffers and circuitry. The circuitry is configured to process a plurality of input values, by identifying each of the input values that is not zero-valued, and, for each value of the identified input values, computing respective products of coefficients of a kernel with the value and storing at least some of the respective products in the buffers. The circuitry is further configured to compute a plurality of output values, by retrieving respective sets of stored values from the buffers, at least some of the retrieved sets including one or more of the products, and summing the retrieved sets. The circuitry is further configured to output the computed output values. Other embodiments are also described.

Abstract: A network interface controller that is connected to a host and a packet communications network. The network interface controller includes electrical circuitry configured as a packet processing pipeline with a plurality of stages. It is determined in the network interface controller that at least a portion of the stages of the pipeline are acceleration-defined stages. Packets are processed in the pipeline by transmitting data to an accelerator from the acceleration-defined stages, performing respective acceleration tasks on the transmitted data in the accelerator, and returning processed data from the accelerator to receiving stages of the pipeline.

Abstract: Communication apparatus includes a host interface and a network interface, which receives at least first and second redundant packet streams, each including a sequence of data packets, which include headers containing respective packet sequence numbers and data payloads of a predefined, fixed size containing respective slices of the data segment. Redundant first and second copies of each slice are transmitted in respective packets in the first and second packet streams. Packet processing circuitry receives the data packets from the network interface, maps the data packets in both the first and second packet streams, using the packet sequence numbers, to respective addresses in a buffer, and writes the data payloads to the respective addresses via the host interface while eliminating redundant data so that the buffer contains exactly one copy of each slice of the data segment, ordered in accordance with the packet sequence numbers.

Abstract: An apparatus includes an input interface and transmit-side circuitry. The input interface is configured to receive a sequence of packets that carries a stream of video frames. The transmit-side circuitry is configured to divide the sequence of packets into multiple interleaved sub-sequences, wherein each sub-sequence carries a respective sub-stream of the stream of video frames, and wherein at least one of the sub-streams is self-contained and viewable independently of any other sub-stream, and to transmit the multiple sub-sequences of packets to a communication network over respective, different packet flows.

Abstract: A network interface controller that is connected to a host and a packet communications network. The network interface controller includes electrical circuitry configured as a packet processing pipeline with a plurality of stages. It is determined in the network interface controller that at least a portion of the stages of the pipeline are acceleration-defined stages. Packets are processed in the pipeline by transmitting data to an accelerator from the acceleration-defined stages, performing respective acceleration tasks on the transmitted data in the accelerator, and returning processed data from the accelerator to receiving stages of the pipeline.

Abstract: Apparatus for data communications includes a host interface and a network interface, which receives from a packet communication network data packets containing video data comprising interleaved words of luminance data and chrominance data. In one embodiment, packet processing circuitry separates the luminance data from the chrominance data and writes the luminance data, via the host interface, to a luminance buffer in the host memory while writing the chrominance data, via the host interface, to at least one chrominance buffer in the memory, separate from the luminance buffer. In another embodiment, in which the video data include data words of more than eight bits, the packet processing circuitry writes the video data to at least one buffer while justifying the video data in the memory so that the video data with respect to successive pixels in the sequence are byte-aligned in the buffer.

Abstract: An apparatus includes an input interface and transmit-side circuitry. The input interface is configured to receive a sequence of packets that carries a stream of video frames. The transmit-side circuitry is configured to divide the sequence of packets into multiple interleaved sub-sequences, wherein each sub-sequence carries a respective sub-stream of the stream of video frames, and wherein at least one of the sub-streams is self-contained and viewable independently of any other sub-stream, and to transmit the multiple sub-sequences of packets to a communication network over respective, different packet flows.

Abstract: Communication apparatus includes a host interface and a network interface, which receives at least first and second redundant packet streams, each including a sequence of data packets, which include headers containing respective packet sequence numbers and data payloads of a predefined, fixed size containing respective slices of the data segment. Redundant first and second copies of each slice are transmitted in respective packets in the first and second packet streams. Packet processing circuitry receives the data packets from the network interface, maps the data packets in both the first and second packet streams, using the packet sequence numbers, to respective addresses in a buffer, and writes the data payloads to the respective addresses via the host interface while eliminating redundant data so that the buffer contains exactly one copy of each slice of the data segment, ordered in accordance with the packet sequence numbers.

Abstract: Described embodiments include a system that includes one or more buffers and circuitry. The circuitry is configured to process a plurality of input values, by identifying each of the input values that is not zero-valued, and, for each value of the identified input values, computing respective products of coefficients of a kernel with the value and storing at least some of the respective products in the buffers. The circuitry is further configured to compute a plurality of output values, by retrieving respective sets of stored values from the buffers, at least some of the retrieved sets including one or more of the products, and summing the retrieved sets. The circuitry is further configured to output the computed output values. Other embodiments are also described.