Abstract: The present invention provides a chip packaging structure and a chip packaging method. Compared with an existing method of joining an encapsulation layer with a dielectric layer, adhesion between the encapsulation layer and a chip in the present invention is increased, and the encapsulation layer is less likely to fall off under stress. Furthermore, during the packaging process, a passivation layer enables chips to be mutually fixed together, which can prevent the chips from being shifted during the encapsulation process, and thereby enhance the reliability of the final product and improve the yield of the final product.

Abstract: A packaging structure, an electronic device, and a packaging method are provided. The packaging structure includes a first packaging module and a second packaging module. The first packaging module includes a first die and a second die, the first die and the second die are arranged in a thickness direction of the first die, and the first die and the second die are electrically connected. The second packaging module and the first packaging module are arranged in the thickness direction, the second packaging module includes a third die and a fourth die, the third die and the fourth die are arranged in the thickness direction, and the third die and the fourth die are electrically connected. The fourth die and the first die are electrically connected.

Abstract: A packaging structure, a method for preparing the packaging structure, and an electronic device are provided. The packaging structure includes a substrate, a first chip, a first conductive member, and a first filling adhesive layer. A groove is provided on the substrate, a first wiring layer is arranged on a bottom wall of the groove, the first chip is arranged in the groove, a first surface of the first chip is electrically connected to the first wiring layer, one end of the first conductive member is electrically connected to the first wiring layer, the first filling adhesive layer is filled in the groove, and the first filling adhesive layer is flush with a surface on which a notch of the groove is located. Both the other end of the first conductive member and a second surface of the first chip are exposed from the first filling adhesive layer.

Abstract: The present invention provides a chip packaging structure and a chip packaging method. Compared with an existing method of joining an encapsulation layer with a dielectric layer, adhesion between the encapsulation layer and a chip in the present invention is increased, and the encapsulation layer is less likely to fall off under stress. Furthermore, during the packaging process, a passivation layer enables chips to be mutually fixed together, which can prevent the chips from being shifted during the encapsulation process, and thereby enhance the reliability of the final product and improve the yield of the final product.