Patents by Inventor Doublas Kemerer

Doublas Kemerer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • IDENTIFYING PARASITIC DIODE(S) IN AN INTEGRATED CIRCUIT PHYSICAL DESIGN
    Publication number: 20070209026
    Abstract: A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.
    Type: Application
    Filed: March 3, 2006
    Publication date: September 6, 2007
    Inventors: Doublas Kemerer, Edward Seibert, Lijiang Wang