Abstract: To increase read reliability margins in read-only MRAM arrays, a complimentary pair of MRAM cells includes a first MRAM cell having a first resistance value within a first “high” resistance range RH and storing a logic “HI” value and a second “shorted” MRAM cell having a second resistance value within a second “minimal” resistance range Ro and storing a logic “LO” value. During manufacture and testing, MRAM cells that are assigned logic “LO” values are permanently shorted prior to distribution such that they permanently exhibit resistance values within the second “minimal” resistance range Ro. When reading the values stored within the complimentary pair of MRAM cells, a differential sense amplifier applies a common reference current across the first MRAM cell and the second “shorted” MRAM cell; by shorting cells with logic “LO” values, a system can reliably read logic values stored within the read-only MRAM array.

Abstract: A multi-bit MRAM cell includes at least a first MTJ device storing a first logic bit and a second MTJ device storing a second logic bit. The multi-bit MRAM cell is readable through application of a reference current across the multi-bit MRAM cell and comparison of a resultant output voltage with a plurality of reference voltages.

Abstract: An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.

Abstract: An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.

Abstract: Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.

Abstract: Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.

Abstract: Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.

Abstract: An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.

Abstract: An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.

Abstract: Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.

Abstract: Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.

Abstract: An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.

Abstract: A top case component of a lead-acid monobloc case that comprises a the top case component comprising a top exterior surface of the monobloc case, wherein the top exterior surface comprises: (a) a pocket configured to house a battery monitor circuit, wherein the pocket extends into an interior of the monobloc case past the sealed interface of the top case component and the primary case component; and (b) at least one pathway configured to house electrically conducting connections that place the battery monitor circuit in electrical connection with the positive and negative terminal poles of the monobloc.

Abstract: Outflow valve (OFV) assemblies including non-metallic frames and enhanced attachment features are provided. In embodiments, the OFV assembly includes a non-metallic frame to which at least one valve door is pivotally mounted. The non-metallic frame may, in turn, include a generally rectangular frame body, a central opening through the frame body, an outer peripheral flange extending around at least a portion of the frame body. Frame attachment interfaces are distributed or spaced around the outer peripheral flange of the non-metallic frame. The frame attachment interfaces include fastener openings and elevated platform regions, which project from an inboard side of the outer peripheral flange and through which the fastener openings extend. Base plates seat against the elevated platform regions. Fasteners engage the base plates and extend through the fastener openings to an outboard side of the outer peripheral flange to attach the OFV assembly to an aircraft fuselage.

Abstract: In certain systems disclosed herein, one or more of a first vascular access port and a second vascular access port can be selected by a customer. Each of the first and second vascular access ports can be implanted subcutaneously within a patient, and each can include a base configured to be attached to a vessel, a body that extends away from the base, and a guidance passageway that extends through the body and the base and includes a funnel region. A maximum height defined by the base and body of the second vascular access port can be greater than a maximum height defined by the base and body of the first vascular access port.

Abstract: Ports for accessing a vessels within a patient include passageways that can guide needles or other access devices directly into the vessels. The ports can be implanted subcutaneously within a patient. Some ports may be used in the creation and use of vascular access buttonholes.

Abstract: Outflow valve (OFV) assemblies including non-metallic frames and enhanced attachment features are provided. In embodiments, the OFV assembly includes a non-metallic frame to which at least one valve door is pivotally mounted. The non-metallic frame may, in turn, include a generally rectangular frame body, a central opening through the frame body, an outer peripheral flange extending around at least a portion of the frame body. Frame attachment interfaces are distributed or spaced around the outer peripheral flange of the non-metallic frame. The frame attachment interfaces include fastener openings and elevated platform regions, which project from an inboard side of the outer peripheral flange and through which the fastener openings extend. Base plates seat against the elevated platform regions. Fasteners engage the base plates and extend through the fastener openings to an outboard side of the outer peripheral flange to attach the OFV assembly to an aircraft fuselage.

Abstract: The philosophy of games is to provide a mental challenge to the person who is playing the game. With this game a person can build the game according to that person's wants and desires and in this case a dodecahedron is used; the dodecahedron is color coded and an interior sphere is placed with the dodecahedron. Clues that have been placed in pockets of the outside surface of the dodecahedron will consist of locations where coins are hidden. These coins will be gathered and the dodecahedron is manipulated. The interior sphere contains the solution to the game or a prize and is initially locked prior to the start of the game. As the contestants play the game and “solve” the puzzle, the interior sphere is unlocked and the solution or prize is revealed. The game can be structured to the desires of the individual builder as often as possible.

Abstract: In certain systems disclosed herein, one or more of a first vascular access port and a second vascular access port can be selected by a customer. Each of the first and second vascular access ports can be implanted subcutaneously within a patient, and each can include a base configured to be attached to a vessel, a body that extends away from the base, and a guidance passageway that extends through the body and the base and includes a funnel region. A maximum height defined by the base and body of the second vascular access port can be greater than a maximum height defined by the base and body of the first vascular access port.

Abstract: In certain systems disclosed herein, one or more of a first vascular access port and a second vascular access port can be selected by a customer. Each of the first and second vascular access ports can be implanted subcutaneously within a patient, and each can include a base configured to be attached to a vessel, a body that extends away from the base, and a guidance passageway that extends through the body and the base and includes a funnel region. A maximum height defined by the base and body of the second vascular access port can be greater than a maximum height defined by the base and body of the first vascular access port.