Abstract: Microelectronic assemblies may include through-assembly conductive vias of varying depth to couple dies or die stacks with one another via a bridge die and/or substrate. In one example, an assembly includes an interconnect structure (e.g., a bridge die) including conductive contacts on a first side and one or more integrated circuit (IC) structures bonded with a second side, where an IC structure includes one or more dies. The assembly may include a first conductive via with a first bottom end in the interconnect structure and a first top end opposite the first bottom end, and a second conductive via with a second bottom end in the interconnect structure and a second top end opposite the second bottom end, where the first top end is in a first plane and the second top end is in a second plane that is different from the first plane.

Abstract: A microelectronic assembly with a bridge die and through-assembly conductive vias may enable higher performance connectivity of dies or die stacks. In one example, an assembly includes a first IC structure (e.g., a bridge die) over and coupled with a circuit board, a second IC structure (e.g., a substrate) over the first IC structure, and a plurality of coplanar dies or die stacks between and bonded with the first IC structure and the second IC structure. Conductive vias may be formed through the dies or die stacks after attaching the dies or die stacks to the first or second IC structures, where a conductive via through a die or die stack may extend through the die or die stack so that a first portion of the conductive via is coplanar with the side or face of the die or die stack that is bonded with the first IC structure.

Abstract: Conductive vias for 3D integration may be formed during or after assembly to couple dies or die stacks. In one example, such conductive vias may extend through the dies or die stacks and through an interface with conductive bumps, without terminating on the bumps. Bypassing conductive bumps with a conductive via may enable improved performance, power delivery, and thermal management. In one example, an assembly includes a first IC structure (such as a substrate, interposer, or other IC structure) and a second IC structure (such as a die or die stack) over the first IC structure. The assembly includes an interface layer between the first IC structure and the second IC structure, where the interface layer includes a plurality of conductive bumps. A conductive via extends through the interface layer with the bumps and is coupled with a conductive element of the first IC structure.

Abstract: Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages. One aspect relates to disaggregating 3D monolithic memory and compute functions to enable tight coupling for fast memory access at high bandwidth. Another aspect relates to microelectronic assemblies relate to nano-TSVs with 3D monolithic memory. Further aspects relate to die stitching and the use of glass carrier structures in microelectronic assemblies. Various aspects disclosed herein advantageously provide a robust set of implementations that may enable significant improvements in terms of optimizing performance of individual IC dies, microelectronic assemblies including one or more of such dies, and IC packages and devices including one or more of such microelectronic assemblies.

Abstract: Moisture hermetic guard ring structures for semiconductor devices, related systems, and methods of fabrication are disclosed. Such devices systems, and methods include a guard ring structure laterally surrounding semiconductor devices of a device layer and metal interconnects of an interconnect layer, the guard ring structure extending through the interconnect layer, the device layer, and a bonding layer adjacent one of the interconnect layer or the device layer the bonding layer, and contacting a support substrate coupled to the bonding layer. Such devices systems, and methods may further include via structures having the same material system as the guard ring structure and also extending through the interconnect, the device, and bonding layers and contacting a support substrate.

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing with modified via-last process are disclosed. The fabrication approach is based on using hybrid manufacturing to bond first and second IC structures originally provided on different dies but filling at least portions of vias that are supposed to couple across a bonding interface between the first and second IC structures with electrically conductive materials after the IC structures have been bonded. A resulting microelectronic assembly that includes the first and second IC structures bonded together may have vias extending through all of the first IC structure and into the second IC structure, thus providing electrical coupling between one or more components of the first IC structure and those of the second IC structure, where an electrically conductive material in the individual vias is continuous through the first IC structure and at least a portion of the second IC structure.

Abstract: Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages. One aspect relates to disaggregating 3D monolithic memory and compute functions to enable tight coupling for fast memory access at high bandwidth. Another aspect relates to microelectronic assemblies relate to nano-TSVs with 3D monolithic memory. Further aspects relate to die stitching and the use of glass carrier structures in microelectronic assemblies. Various aspects disclosed herein advantageously provide a robust set of implementations that may enable significant improvements in terms of optimizing performance of individual IC dies, microelectronic assemblies including one or more of such dies, and IC packages and devices including one or more of such microelectronic assemblies.

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.

Abstract: Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages, related to direct chip attach of dies and circuit boards. An example microelectronic assembly includes a die with IC components provided over the die's frontside, and a metallization stack provided over the die's backside. The die further includes die interconnects extending between the frontside and the backside of the die, to electrically couple the IC components and the metallization stack. The assembly further includes backside conductive contacts, provided over the side of the metallization stack facing away from the die, the backside conductive contacts configured to route signals to/from the IC components via the metallization stack and the die interconnects, and configured to be coupled to respective conductive contacts of a circuit board in absence of a package substrate between the die and the circuit board.

Abstract: Moisture hermetic guard ring structures for semiconductor devices, related systems, and methods of fabrication are disclosed. Such devices systems, and methods include a guard ring structure laterally surrounding semiconductor devices of a device layer and metal interconnects of an interconnect layer, the guard ring structure extending through the interconnect layer, the device layer, and a bonding layer adjacent one of the interconnect layer or the device layer the bonding layer, and contacting a support substrate coupled to the bonding layer. Such devices systems, and methods may further include via structures having the same material system as the guard ring structure and also extending through the interconnect, the device, and bonding layers and contacting a support substrate.

Abstract: Moisture hermetic guard ring structures for semiconductor devices, related systems, and methods of fabrication are disclosed. Such devices systems, and methods include a guard ring structure laterally surrounding semiconductor devices of a device layer and metal interconnects of an interconnect layer, the guard ring structure extending through the interconnect layer, the device layer, and a bonding layer adjacent one of the interconnect layer or the device layer the bonding layer, and contacting a support substrate coupled to the bonding layer. Such devices systems, and methods may further include via structures having the same material system as the guard ring structure and also extending through the interconnect, the device, and bonding layers and contacting a support substrate.

Abstract: Embodiments may relate to a microelectronic package. The microelectronic package may include a memory die with: a first memory cell at a first layer of the memory die; a second memory cell at a second layer of the memory die; and a via in the memory die that communicatively couples an active die with a package substrate of the microelectronic package. Other embodiments may be described or claimed.

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing with modified via-last process are disclosed. The fabrication approach is based on using hybrid manufacturing to bond first and second IC structures originally provided on different dies but filling at least portions of vias that are supposed to couple across a bonding interface between the first and second IC structures with electrically conductive materials after the IC structures have been bonded. A resulting microelectronic assembly that includes the first and second IC structures bonded together may have vias extending through all of the first IC structure and into the second IC structure, thus providing electrical coupling between one or more components of the first IC structure and those of the second IC structure, where an electrically conductive material in the individual vias is continuous through the first IC structure and at least a portion of the second IC structure.

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.

Abstract: Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages, related to direct chip attach of dies and circuit boards. An example microelectronic assembly includes a die with IC components provided over the die's frontside, and a metallization stack provided over the die's backside. The die further includes die interconnects extending between the frontside and the backside of the die, to electrically couple the IC components and the metallization stack. The assembly further includes backside conductive contacts, provided over the side of the metallization stack facing away from the die, the backside conductive contacts configured to route signals to/from the IC components via the metallization stack and the die interconnects, and configured to be coupled to respective conductive contacts of a circuit board in absence of a package substrate between the die and the circuit board.