Patents by Inventor Doug Den Dulk

Doug Den Dulk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Layout versus schematic error system and method
    Patent number: 8397194
    Abstract: According to various embodiments of the invention, systems and methods for presenting Layout Versus Schematic (LVS) errors within a layout using a visual circuit representation of the design and highlighting is provided. One embodiment includes overlaying the layout circuit representation on the schematic circuit representation with highlighting that indicates the LVS errors. The method of such an embodiment compares a layout netlist against a schematic netlist in order to identify the layout-versus-schematic errors, generates a graphical representation of the layout netlist and a graphical representation of the schematic netlist, displays an overlay of the graphical representation of the layout netlist with the graphical representation of the schematic netlist and then, highlights the identified layout-versus-schematic errors that are present.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: March 12, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Prasanti Uppaluri, Doug Den Dulk
  • LAYOUT VERSUS SCHEMATIC ERROR SYSTEM AND METHOD
    Publication number: 20120227024
    Abstract: According to various embodiments of the invention, systems and methods for presenting Layout Versus Schematic (LVS) errors within a layout using a visual circuit representation of the design and highlighting is provided. One embodiment includes overlaying the layout circuit representation on the schematic circuit representation with highlighting that indicates the LVS errors. The method of such an embodiment compares a layout netlist against a schematic netlist in order to identify the layout-versus-schematic errors, generates a graphical representation of the layout netlist and a graphical representation of the schematic netlist, displays an overlay of the graphical representation of the layout netlist with the graphical representation of the schematic netlist and then, highlights the identified layout-versus-schematic errors that are present.
    Type: Application
    Filed: May 14, 2012
    Publication date: September 6, 2012
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Prasanti UPPALURI, Doug Den DULK
  • Layout versus schematic error system and method
    Patent number: 8181137
    Abstract: According to various embodiments of the invention, systems and methods for presenting Layout Versus Schematic (LVS) errors within a layout using a visual circuit representation of the design and highlighting is provided. One embodiment includes overlaying the layout circuit representation on the schematic circuit representation with highlighting that indicates the LVS errors. The method of such an embodiment compares a layout netlist against a schematic netlist in order to identify the layout-versus-schematic errors, generates a graphical representation of the layout netlist and a graphical representation of the schematic netlist, displays an overlay of the graphical representation of the layout netlist with the graphical representation of the schematic netlist and then, highlights the identified layout-versus-schematic errors that are present.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: May 15, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Prasanti Uppaluri, Doug Den Dulk
  • LAYOUT VERSUS SCHEMATIC ERROR SYSTEM AND METHOD
    Publication number: 20090064077
    Abstract: According to various embodiments of the invention, systems and methods for presenting Layout Versus Schematic (LVS) errors within a layout using a visual circuit representation of the design and highlighting is provided. One embodiment includes overlaying the layout circuit representation on the schematic circuit representation with highlighting that indicates the LVS errors. The method of such an embodiment compares a layout netlist against a schematic netlist in order to identify the layout-versus-schematic errors, generates a graphical representation of the layout netlist and a graphical representation of the schematic netlist, displays an overlay of the graphical representation of the layout netlist with the graphical representation of the schematic netlist and then, highlights the identified layout-versus-schematic errors that are present.
    Type: Application
    Filed: September 4, 2008
    Publication date: March 5, 2009
    Inventors: Prasanti Uppaluri, Doug Den Dulk