Abstract: A circuit which facilitates TDF testing without having to purchase expensive new test equipment, such as a new test platform that is capable of supporting test frequencies well beyond the current 200 MHz limitation. A solution to current TDF testing problems by adding circuitry to the device-under-test (DUT) that is configured to receive two reference clock signals from automated test equipment (ATE), i.e. conventional ATE which does not provide test frequencies beyond 200 Mhz, and create two high-speed clock pulses that serve as the launch and capture clocks for the TDF test sequence on the DUT.

Abstract: A circuit which facilitates TDF testing without having to purchase expensive new test equipment, such as a new test platform that is capable of supporting test frequencies well beyond the current 200 MHz limitation. A solution to current TDF testing problems by adding circuitry to the device-under-test (DUT) that is configured to receive two reference clock signals from automated test equipment (ATE), i.e. conventional ATE which does not provide test frequencies beyond 200 Mhz, and create two high-speed clock pulses that serve as the launch and capture clocks for the TDF test sequence on the DUT.

Abstract: A measurement technique which allows the error components of the testing process to be eliminated by performing a differential-style measurement of the programmable termination resistor network. Since for any given DUT pin which is to be tested, there are multiple possible resistances to be measured, the test process provides that two or more resistance measurements are taken on the same pin. Once those values containing the error components are obtained, they are compared to generate a differential resistance measurement which contains only the actual on-chip DUT resistance with the error components completely removed. The differential value can then be tested against previously defined test limits that are set to guarantee the conformance of the on-chip resistance to the processing specifications. The technique can be applied at either the wafer sort or package test phase of device testing, with the different error components associated with either phase being eliminated.

Abstract: A measurement technique which allows the error components of the testing process to be eliminated by performing a differential-style measurement of the programmable termination resistor network. Since for any given DUT pin which is to be tested, there are multiple possible resistances to be measured, the test process provides that two or more resistance measurements are taken on the same pin. Once those values containing the error components are obtained, they are compared to generate a differential resistance measurement which contains only the actual on-chip DUT resistance with the error components completely removed. The differential value can then be tested against previously defined test limits that are set to guarantee the conformance of the on-chip resistance to the processing specifications. The technique can be applied at either the wafer sort or package test phase of device testing, with the different error components associated with either phase being eliminated.