Abstract: Embodiments of a multi-stage clock generator architecture that generates multiple non-overlapping clock phase signals includes: a first stage clock generator configured to: divide an input clock signal into a number of clock signals, synchronize each clock signal to a transition edge of a synchronization signal to produce synchronized clock signals, wherein the synchronization signal is a delayed version of the input clock signal by at least an amount sufficient to ensure that each of the clock signals become stable in response to a transition edge of the input clock signal, and generate a number of clock phase signals based on the synchronized clock signals. The architecture also includes a later stage clock generator configured to: generate a set of mutually non-overlapping clock phase signals based on the input clock signal.

Abstract: Embodiments of a multi-channel analog to digital converter (ADC) include: a first multiplying digital to analog converter (MDAC) having: first and second switched capacitor circuit paths respectively coupled between first and second input nodes and an input node of a first gain element, a second MDAC having: third and fourth switched capacitor circuit paths respectively coupled between third and fourth input nodes and an input node of a second gain element, a third MDAC having: fifth and sixth switched capacitor circuit paths respectively coupled between a fifth input node and an input node of a third gain element, seventh and eighth switched capacitor circuit paths respectively coupled between a sixth input node and the input node of the third gain element, the fifth input node coupled to an output node of the first gain element, the sixth input node coupled to an output node of the second gain element.

Abstract: A circuit and method for reducing voltage error when charging and discharging a storage capacitor (44) through a transmission gate (43). The storage capacitor (44) stores or holds a voltage coupled through the transmission gate (43) when the transmission gate (43) is disabled. The circuit comprises a clock generation circuit (47) providing complementary clock signals for enabling and disabling the transmission gate (43) and a charge negating transmission gate (46). The clock generation circuit (47) provides the complementary clock signals simultaneously to the transmission gates (43, 46). Alternate paths for dissipating channel charge of the transistors which comprise the transmission gate (43) are not formed by providing the complementary clock signals simultaneously. The channel charge is then canceled by the charge negating transmission gate (46) reducing voltage error on the storage capacitor (44).

Abstract: A circuit and method for reducing voltage error when charging and discharging a variable capacitor (44) through a switch (43). The switch (43) comprises a plurality of transmission gates (53-55) coupled in parallel. A control circuit (42) provides control signals for enabling transmission gates of the plurality of transmission gates (53-55). The control circuit (42) changes the resistance of the switch (43) by selecting an appropriate transmission gate wherein each transmission gate has a different resistance. The resistance of the switch (43) is varied as a capacitance of the variable capacitor (44) is changed to maintain a predetermined RC time constant over the entire range of capacitor values of the variable capacitor (44).