Patents by Inventor Doug H. Lee

Doug H. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8173530
    Abstract: A semiconductor device and related method of fabricating it are provided. An exemplary fabrication process begins by forming a gate structure overlying a layer of semiconductor material, the gate structure comprising a gate insulator overlying the layer of semiconductor material and comprising a temporary gate element overlying the gate insulator. The process continues by forming a layer of compressive material overlying the gate structure, and by removing a first portion of the compressive material to expose an upper surface of the temporary gate element, while leaving a second portion of the compressive material intact and external to sidewalls of the temporary gate element. Thereafter, at least a portion of the temporary gate element is removed, while leaving the second portion of the compressive material intact, resulting in a gate recess. The process continues by at least partially filling the gate recess with a gate electrode material.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: May 8, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Doug H. Lee, Kisik Choi
  • Patent number: 8071485
    Abstract: Small feature patterning is accomplished using a multilayer hard mask (HM). Embodiments include sequentially forming a first HM layer and a multilayer HM layer over a substrate, the multilayer HM layer comprising sublayers, etching the multilayer HM layer to form a first opening having an upper first opening with sides converging to a lower second opening and a second opening with substantially parallel sides and an opening substantially corresponding to the lower second opening of the first opening, etching through the second opening to form a corresponding opening in the first HM layer, and etching the substrate through the corresponding opening in the first HM layer.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: December 6, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Doug H. Lee, Erik P. Geiss
  • Publication number: 20100327412
    Abstract: Small feature patterning is accomplished using a multilayer hard mask (HM). Embodiments include sequentially forming a first HM layer and a multilayer HM layer over a substrate, the multilayer HM layer comprising sublayers, etching the multilayer HM layer to form a first opening having an upper first opening with sides converging to a lower second opening and a second opening with substantially parallel sides and an opening substantially corresponding to the lower second opening of the first opening, etching through the second opening to form a corresponding opening in the first HM layer, and etching the substrate through the corresponding opening in the first HM layer.
    Type: Application
    Filed: June 29, 2009
    Publication date: December 30, 2010
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Doug H. Lee, Erik P. Geiss
  • Publication number: 20100301401
    Abstract: A semiconductor device and related method of fabricating it are provided. An exemplary fabrication process begins by forming a gate structure overlying a layer of semiconductor material, the gate structure comprising a gate insulator overlying the layer of semiconductor material and comprising a temporary gate element overlying the gate insulator. The process continues by forming a layer of compressive material overlying the gate structure, and by removing a first portion of the compressive material to expose an upper surface of the temporary gate element, while leaving a second portion of the compressive material intact and external to sidewalls of the temporary gate element. Thereafter, at least a portion of the temporary gate element is removed, while leaving the second portion of the compressive material intact, resulting in a gate recess. The process continues by at least partially filling the gate recess with a gate electrode material.
    Type: Application
    Filed: June 1, 2009
    Publication date: December 2, 2010
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Doug H. Lee, Kisik Choi
  • Patent number: 7601645
    Abstract: Methods for fabricating devices having small feature sizes are provided. In an exemplary embodiment, a method comprises forming a patterned first mask layer overlying a subject material layer and isotropically etching the patterned first mask layer. A second masking layer is deposited overlying the patterned first mask layer and the isotropically-etched patterned first mask layer is exposed. The isotropically-etched patterned first mask layer is removed and the subject material layer is etched to form a feature therein.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: October 13, 2009
    Assignee: Globalfoundries Inc.
    Inventors: Doug H. Lee, Andreas Knorr
  • Publication number: 20080179281
    Abstract: Methods for fabricating devices having small feature sizes are provided. In an exemplary embodiment, a method comprises forming a patterned first mask layer overlying a subject material layer and isotropically etching the patterned first mask layer. A second masking layer is deposited overlying the patterned first mask layer and the isotropically-etched patterned first mask layer is exposed. The isotropically-etched patterned first mask layer is removed and the subject material layer is etched to form a feature therein.
    Type: Application
    Filed: October 15, 2007
    Publication date: July 31, 2008
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Doug H. Lee, Andreas Knorr
  • Patent number: 7297636
    Abstract: Methods for fabricating devices having small feature sizes are provided. In an exemplary embodiment, a method comprises forming a patterned first mask layer overlying a subject material layer and isotropically etching the patterned first mask layer. A second masking layer is deposited overlying the patterned first mask layer and the isotropically-etched patterned first mask layer is exposed. The isotropically-etched patterned first mask layer is removed and the subject material layer is etched to form a feature therein.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: November 20, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Doug H. Lee, Andreas Knorr