Patents by Inventor Doug Ingerly

Doug Ingerly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210013188
    Abstract: Systems and methods for providing a low profile stacked die semiconductor package in which a first semiconductor package is stacked with a second semiconductor package and both semiconductor packages are conductively coupled to an active silicon substrate that communicably couples the first semiconductor package to the second semiconductor package. The first semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a first interconnect pattern having a first interconnect pitch. The second semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a second interconnect pattern having a second pitch that is greater than the first pitch. The second semiconductor package may be stacked on the first semiconductor package and conductively coupled to the active silicon substrate using a plurality of conductive members or a plurality of wirebonds.
    Type: Application
    Filed: September 28, 2017
    Publication date: January 14, 2021
    Applicant: Intel Corporation
    Inventors: Wilfred Gomes, Sanka Ganesan, DOUG INGERLY, ROBERT SANKMAN, MARK BOHR, DEBENDRA MALLIK
  • Patent number: 10872820
    Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: December 22, 2020
    Assignee: Intel Corporation
    Inventors: Bruce Block, Valluri R. Rao, Patrick Morrow, Rishabh Mehandru, Doug Ingerly, Kimin Jun, Kevin O'Brien, Paul Fischer, Szyua S. Liao
  • Publication number: 20200258852
    Abstract: Techniques and mechanisms for providing an inductor with an integrated circuit (IC) die. In an embodiment, the IC die comprises integrated circuitry and one or more first metallization layers. The IC die is configured to couple to a circuit device including one or more second metallization layers, where such coupling results in the formation of an inductor which is coupled to the integrated circuitry. One or more loop structures of the inductor each span both some or all of the one or more first metallization layers and some or all of the one or more second metallization layers. In another embodiment, the IC die or the circuit device includes a ferromagnetic material to concentrate a magnetic flux which is provided with the inductor.
    Type: Application
    Filed: September 29, 2017
    Publication date: August 13, 2020
    Inventors: Wilfred GOMES, Mark BOHR, Doug INGERLY, Rajesh KUMAR, Harish KRISHNAMURTHY, Nachiket Venkappayya DESAI
  • Publication number: 20200194540
    Abstract: An inductor is disclosed. The inductor includes a vertically coiled conductor, a metal contact coupled to a first end of the vertically coiled conductor, and a dielectric material coupled to the metal contact. A tunable high permittivity component is coupled to a second end of the vertically coiled conductor.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: Gwang-Soo KIM, Aaron D. LILAK, Kumhyo BYON, Doug INGERLY
  • Publication number: 20200066679
    Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.
    Type: Application
    Filed: December 21, 2017
    Publication date: February 27, 2020
    Inventors: Mark T. BOHR, Wilfred GOMES, Rajesh KUMAR, Pooya TADAYON, Doug INGERLY
  • Publication number: 20200035560
    Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.
    Type: Application
    Filed: August 25, 2017
    Publication date: January 30, 2020
    Applicant: Intel Corporation
    Inventors: Bruce BLOCK, Valluri R. RAO, Patrick MORROW, Rishabh MEHANDRU, Doug INGERLY, Kimin JUN, Kevin O'BRIEN, Patrick MORROW, Szyua S. LIAO
  • Patent number: 8154121
    Abstract: Polymer interlayer dielectric and passivation materials for a microelectronic device are generally described. In one example, an apparatus includes one or more interconnect structures of a microelectronic device and one or more polymeric dielectric layers coupled with the one or more interconnect structures, the polymeric dielectric layers including copolymer backbones having a first monomeric unit and a second monomeric unit wherein the first monomeric unit has a different chemical structure than the second monomeric unit and wherein the copolymer backbones are cross-linked by a first cross-linker or a second cross-linker, or combinations thereof.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: April 10, 2012
    Assignee: Intel Corporation
    Inventors: Kunal Shah, Michael Haverty, Sadasivan Shankar, Doug Ingerly, Grant Kloster
  • Publication number: 20090212421
    Abstract: Polymer interlayer dielectric and passivation materials for a microelectronic device are generally described. In one example, an apparatus includes one or more interconnect structures of a microelectronic device and one or more polymeric dielectric layers coupled with the one or more interconnect structures, the polymeric dielectric layers including copolymer backbones having a first monomeric unit and a second monomeric unit wherein the first monomeric unit has a different chemical structure than the second monomeric unit and wherein the copolymer backbones are cross-linked by a first cross-linker or a second cross-linker, or combinations thereof.
    Type: Application
    Filed: February 26, 2008
    Publication date: August 27, 2009
    Inventors: Kunal Shah, Michael Haverty, Sadasivan Shankar, Doug Ingerly, Grant Kloster