Abstract: In general, the invention relates to a business intelligence platform. In one aspect, data is logged such that information about execution instances can be obtained. In another aspect, action sequences are developed, stored, and executed, such that use of a variety of components can be specified.

Abstract: Methods and apparatus for inbound PCI configuration cycles are disclosed. By definition, PCI bridges block upstream progress of configuration cycles initiated by a PCI bus master on their secondary buses. In the described embodiments, a PCI bus master can execute a configuration cycle despite this limitation, by converting the configuration cycle command to Memory Read and Write commands that a PCI bridge will forward upstream. The PCI bus master writes the address of a target configuration register to a first predefined address, and pushes or pulls data from that target register by subsequently initiating a memory access to a second predefined address. A platform chipset is designed to recognize Memory Read and Write accesses to the predefined addresses as relating to an inbound configuration cycle. When a memory access to the second address is received, the chipset uses the information stored at the first address to form and execute a configuration cycle on behalf of the downstream PCI bus master.

Abstract: A graphics digitizer having a phase-locked-loop, a timing generator, and at least one channel with a reference and bias voltage generator and an analog-to-digital converter is disclosed. In some embodiments, the phase-locked-loop includes a programmable Div/N circuit so that the output frequency of the signal generated by the phase-locked-loop is programmable. In some embodiments, the timing generator generates a HSOUT video signal in response to the HSYNC video signal by sampling the HSYNC video signal with a phase adaptively chosen in response to a programmable phase between the signal generated by the phase-locked-loop and the HSYNC video signal. In some embodiments of the invention the reference and bias voltage generates a reference voltage determined by a digital-to-analog conversion of a value stored in a programmable gain register and generates a bias voltage proportionally to the reference voltage by a current digital-to-analog conversion of a value stored in a programmable offset register.

Abstract: Methods and apparatus for inbound PCI configuration cycles are disclosed. By definition, PCI bridges block upstream progress of configuration cycles initiated by a PCI bus master on their secondary buses. In the described embodiments, a PCI bus master can execute a configuration cycle despite this limitation, by converting the configuration cycle command to Memory Read and Write commands that a PCI bridge will forward upstream. The PCI bus master writes the address of a target configuration register to a first predefined address, and pushes or pulls data from that target register by subsequently initiating a memory access to a second predefined address. A platform chipset is designed to recognize Memory Read and Write accesses to the predefined addresses as relating to an inbound configuration cycle. When a memory access to the second address is received, the chipset uses the information stored at the first address to form and execute a configuration cycle on behalf of the downstream PCI bus master.

Abstract: A computer system includes a host processor coupled to a host bus. A bridge controller is coupled to the host bus and to a plurality of first buses. The computer system also includes one or more bus bridges, each coupled to the bridge controller via one or more of said first buses. Each bus bridge is connected to one or more second buses. Either the first buses or the second buses are each configurable in either an independent mode in which the bus operates independently, or a combined mode in which two or more of said first buses or said second buses are combined to create a single bus.