Abstract: A device may include a digital-to-analog converter (DAC), including a current source, circuitry to mirror the current source, the circuitry including a transistor coupled to the current source, and a plurality of output paths, each output path of the plurality of output paths including a first switch to selectively configure a first transistor to mirror the current source, wherein each output path corresponds to a value of a respective bit of a first digital signal, and a plurality of cells, each cell of the plurality of cells including a second switch to selectively couple a second transistor to a corresponding one of the plurality of output paths, wherein each of the plurality of cells corresponds to a value of a respective bit of a second digital signal.

Abstract: A method and apparatus for providing high speed, linear-phase interpolation. Signals from a plurality of differential pairs are weighted to produce an output clock having a selectable linear phase variation. A controller includes a pulse generator for providing a predetermined number of pulses having a predetermined phase shift and a predetermined frequency and an interpolator for processing the predetermined number of pulses having a predetermined phase shift and a predetermined frequency to generate a clock signal that is linearly adjustable between a predetermined number of output phases.

Abstract: A method and apparatus for providing high speed, linear-phase interpolation. Signals from a plurality of differential pairs are weighted to produce an output clock having a selectable linear phase variation. A controller includes a pulse generator for providing a predetermined number of pulses having a predetermined phase shift and a predetermined frequency and an interpolator for processing the predetermined number of pulses having a predetermined phase shift and a predetermined frequency to generate a clock signal that is linearly adjustable between a predetermined number of output phases.