Abstract: A method comprising: activating a strobed or pulsed illumination source to produce illuminating light; polarising the illuminating light in a first polarisation axis; illuminating at least part of a tall plant crop with the polarised illuminating light to produce reflected illuminating light; polarising the reflected illuminating light in a second polarisation axis transverse to the first polarisation axis produce cross-polarised reflected illuminating light; capturing an image of at least part of the tall plant crop using the cross-polarised reflected illuminating light; and analysing the captured image to determine a condition of the tall plant crop. Also a vehicle mounted image capture system, a vehicle mounted spraying system and a plant health management system.

Abstract: Disclosed is an olfaction system based on integration of gas sensitive conducting polymers and Floating Gate Metal Oxide Semiconductor (FGMOS) sensors. A sensing polymer, polypyrrole for example, is electrochemically deposited onto sensor pads which are electrically connected to floating gate of the sensor. The response of these sensing polymers to any vapour analyte can be tailored using several techniques that include the use of different dopants, changing electrolyte concentrations or varying growth potential at the time of electrodeposition. Using an array of floating gate sensors, coupled to these chemically diverse polymers, this system will facilitate a signature-like response from the sensors in the array. Every sensor can be accessed and analysed individually using a specially designed addressing circuit. The response from the sensors is amplified through a trans-impedance amplifier and converted to 8-bit digital data for ease of analyte identification and quantification.

Abstract: A capacitive micromachined ultrasonic transducer (CMUT) having at least two deflectable membranes. The membranes are spaced from each other, and the membranes contribute to and/or are responsive to receive or transmit an ultrasonic signal. Spacing between the at least two deflectable membranes is adjustable through application of a voltage to cause deflection of at least one of the deflectable membranes, to affect the receive/transmit properties of the CMUT.

Abstract: A capacitive micromachined ultrasonic transducer (CMUT) having at least two deflectable membranes. The membranes are spaced from each other, and the membranes contribute to and/or are responsive to receive or transmit an ultrasonic signal. Spacing between the at least two deflectable membranes is adjustable through application of a voltage to cause deflection of at least one of the deflectable membranes, to affect the receive/transmit properties of the CMUT.

Abstract: The present invention teaches a flame retardation composition. The composition comprises: Ammonium Polyphosphate, Sodium Borate, Boric Acid, 3% Hydrogen Peroxide Solution used as Biocide, and Distilled Water. A homogeneous flame retarding composition solution is processed by mixing the referenced composition compounds in distilled water. The flame retarding composition solution is coated on to be protected substrate surfaces against flame retardation. The materials coated with flame retarding composition solution fully satisfy flammability test under the Federal Aviation Regulation (FAR) 25.853(a) vertical burn test, and Federal Aviation Regulation (FAR) 25.853(d) heat release test. The utility of the present invention extends to numerous commercial and non-commercial applications.

Abstract: The present invention teaches a three-step method for an aqua based chemical composition for flame retardation. The composition comprises: Sodium Borate, Boric Acid, Guanylurea Phosphate, Hydrogen Peroxide, Magnesium Chloride, and Sodium Silicate. The referenced salts are dissolved in distilled water, and the resultant flame retarding solution is coated on substrate surfaces to be protected against flame retardation. The flame retarding composition solution from step-1 alone may be used on non-prepared substrate surfaces. The flame retarding composition solution fully satisfies the Federal Aviation Regulation (FAR) 25.853(a) vertical burn test, and Federal Aviation Regulation (FAR) 25.853(d) heat release test. The utility of the present invention extends to numerous commercial and non-commercial applications.

Abstract: The present invention teaches an acrylic or latex comprising flame retarding composition. The composition comprises: Sodium polyacrylates, Acrylic Polymer Solution, Silicone Surfactant, Titanium Dioxide Pigment, Ammonium Polyphosphate, Mono-Pentacrythritol, Melamine powder, Hydrogen Peroxide, Hydroxyethyl Cellulose, Ester Alcohol, Acrylic Copolymer Emulsion, Soda Lime Borosilicate Glass, Hydrophobically Modified Ethylene Oxide Urethane and Distilled Water. The flame retarding composition fully satisfies the Federal Aviation Regulation (FAR) 25.853(a) vertical burn test, and Federal Aviation Regulation (FAR) 25.853(d) heat release test. The acrylic or latex comprising flame retarding composition is equally useful for prepared or non-prepared substrate surfaces. The utility of the present invention extends to numerous commercial and non-commercial applications.

Abstract: The present invention teaches a three-step method for an aqua based chemical composition for flame retardation. The composition comprises: Sodium Borate, Boric Acid, Guanylurea Phosphate, Hydrogen Peroxide, Magnesium Chloride, and Sodium Silicate. The referenced salts are dissolved in distilled water, and the resultant flame retarding solution is coated on substrate surfaces to be protected against flame retardation. The flame retarding composition solution from step-1 alone may be used on non-prepared substrate surfaces. The flame retarding composition solution fully satisfies the Federal Aviation Regulation (FAR) 25.853(a) vertical burn test, and Federal Aviation Regulation (FAR) 25.853(d) heat release test. The utility of the present invention extends to numerous commercial and non-commercial applications.

Abstract: Methods for the aqueous oxidation of metallic films are described. For example, a film of hafnium metal on a silicon substrate can be oxidized to hafnium dioxide using hot deionized water. Methods for fabricating electrical components such as capacitors and field effect transistors using the oxidized metallic films are also described. For example, capacitors having a hafnium dioxide dielectric layer can be fabricated.

Abstract: A system and method for patterning metal oxide materials in a semiconductor structure. The method comprises a first step of depositing a layer of metal oxide material over a substrate. Then, a patterned mask layer is formed over the metal oxide layer leaving one or more first regions of the metal oxide layer exposed. The exposed first regions of the metal oxide layer are then subjected to an energetic particle bombardment process to thereby damage the first regions of the metal oxide layer. The exposed and damaged first regions of the metal oxide layer are then removed by a chemical etch. Advantageously, the system and method is implemented to provide high-k dielectric materials in small-scale semiconductor devices. Besides using the ion implantation damage (I/I damage) plus wet etch technique to metal oxides (including metal oxides not previously etchable by wet methods), other damage methods including lower energy, plasma-based ion bombardment, may be implemented.

Abstract: A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.

Abstract: A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.

Abstract: Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds.

Abstract: A semiconductor structure, particularly a gate stack, useful in field effect transistors (FETs) in which the threshold voltage thereof is controlled by introducing a fixed spatial distribution of electric charge density to the gate dielectric material and a method of forming the same are provided. nFETs and/or pFETs structures are disclosed. In accordance with the present invention, the fixed spatial distribution of electric charge density of the gate stack or FET denotes an electrical charge density that occupies space which remains substantially constant as a function of time under device operation conditions and is non-zero at least at one location within the dielectric material or at its interface with the channel, gate electrode, spacer, or any other structural elements of the device.

Abstract: Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds.

Abstract: Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds.

Abstract: A precursor source mixture useful for CVD or ALD of a film comprising: at least one precursor composed of an element selected from the group consisting of Li, Na, K, Rb, Cs, Fr, Be, Mg, Ti, Zr, Hf, Sc, Y, La, V, Nb, Ta, Cr, Mo, W, Mn, Re, Fe, Ru, Os, Co, Rh, Ir, Ni, Pd, Pt, Cu, Ag, Au, Zn, Cd, Hg, B, Al, Ga, In, Tl, Si, Ge, Sn, Pb, As, P, Sb and Bi, to which is bound at least one ligand selected from the group consisting of hydride, alkyl, alkenyl, cycloalkenyl, aryl, alkyne, carbonyl, amido, imido, hydrazido, phosphido, nitrosyl, nitryl, nitrate, nitrile, halide, azide, alkoxy, siloxy, silyl, and halogenated, sulfonated or silyated derivatives thereof, which is dissolved, emulsified or suspended in an inert liquid selected from the group consisting of aliphatic hydrocarbons, aromatic hydrocarbons, alcohols, ethers, aldehydes, ketones, acids, phenols, esters, amines, alkylnitrile, halogenated hydrocarbons, silyated hydrocarbons, thioethers, amines, cyanates, isocyanates, thiocyanates, silicone oils, nitroalky

Abstract: Methods of forming front-end-of the line (FEOL) capacitors such as polysilicon-polysilicon capacitors and metal-insulator-silicon capacitors are provided that are capable of incorporating a high-dielectric constant (k of greater than about 8) into the capacitor structure. The inventive methods provide high capacitance/area devices with low series resistance of the top and bottom electrodes for high frequency responses. The inventive methods provide a significant reduction in chip size, especially in analog and mixed-signal applications where large areas of capacitance are used.

Abstract: A method (and resultant structure) of forming a semiconductor structure, includes forming a mixed rare earth oxide on silicon. The mixed rare earth oxide is lattice-matched to silicon.

Abstract: An apparatus and method of forming an oxynitride insulating layer on a substrate performed by putting the substrate at a first temperature within the main chamber of a furnace, exposing the substrate to a nitrogen containing gas at a second temperature which is higher than the first temperature, and growing the oxynitride layer on the substrate within the main chamber in the presence of post-combusted gases. The higher temperature nitrogen containing gases are combusted in a chamber outside the main chamber. The higher temperature is in the range of 800 to 1200° C., and preferably 950° C. In a second embodiment, distributed N2O gas injectors within the main chamber deliver the nitrogen containing gas. The nitrogen containing gas is pre-heated outside the chamber. The nitrogen containing gas is then delivered to a gas manifold that splits the gas flow and directs the gas to a number of gas injectors, preferably two to four injectors within the main process tube.