Abstract: A switchable current source (41) for a Digital to Analog Converter (DAC) to reduce noise glitches when a change in total current provided by the DAC occurs. The switchable current source (41) is one of many required by a DAC to convert a digital signal to an analog signal. Each current source of the DAC receives an input voltage that enables or disables the current source from providing or not providing a current. A sampled input voltage is alternately provided to the switchable current source (41) by a first flip flop (42) or a second flip flop (43). One flip flop samples the input voltage while the other provides a previous sampled input voltage for enabling and disabling the switchable current source (41). Switches (46,47) couple an output voltage of the first or second flip flops (42,43) a predetermined time after the output voltage changes to a transistor (51) coupled to a current source (53).

Abstract: A programmable capacitor array (10, 10') and a method for programming the programmable capacitor array (10, 10'). The programmable capacitor array (10, 10') includes an array of capacitors (C.sub.0 -C.sub.n), wherein each capacitor of the array of capacitors (C.sub.0 -C.sub.n) has first and second terminals. The first terminal of each capacitor may be coupled to a first circuit node (11) or to a first reference terminal (13). Likewise, the second terminal of each capacitor may be coupled to a second circuit node (12) or to a second reference terminal (14). One or more capacitors of the array of capacitors (C.sub.0 -C.sub.n) may be selectively coupled across the first (11) and second (12) circuit nodes or coupled across the first (13) and second (14) reference terminals, thereby permitting each capacitor to be electrically isolated from the array of capacitors (C.sub.0 -C.sub.n).

Abstract: A switched capacitor gain stage (21) that samples an input voltage every clock cycle phase for effectively doubling the frequency of operation. The switched capacitor gain stage (21) comprising an amplifier (22), a first capacitor network, and a second capacitor network. Either the first or second capacitor network is sampling an input voltage. For example, the first capacitor network samples an input voltage. Capacitors of the first capacitor network are coupled to sample the input voltage via switches. Capacitors of the second switched capacitor network are coupled around the amplifier (22) in a gain configuration via switches. The capacitors of the second switched capacitor network having a voltage stored from a previous clock phase. In a next clock phase the second switched capacitor network are coupled via switches for sampling an input voltage and the first switched capacitor network is coupled via switches in a gain configuration around the amplifier (22).

Abstract: Comparator circuit (72) samples a differential input signal at switched capacitor circuit (100). The input signal is stored across capacitors (128, 130, 132, 134). Reference voltages are subtracted from the input signal to produce a difference signal. The difference is compared to a mid-supply reference VMID, and an amplified representation of the signal is produced at the output of differential gain stage (136). Latching output stage (138) uses feedback circuits (204, 211 and 202, 208) to process the amplified signal and to produce a rail to rail representation of the amplified signal at the inputs (146, 148) of SR latch (140). The feedback circuit also powers-down the output stage after processing the amplified signal. Buffer circuits (205, 213 and 214, 212) allow a new signal to be processed by capacitor circuit (100) while the previous signal is being stored in the SR latch.