Abstract: A new programmable weak write circuit is defined with the ability to perform SRAM weak write testing at multiple stress strength settings which track process variation. Prior art weak write test circuitry is designed to test a population of SRAM devices at a fixed weak write stress strength as determined by the best available pre-silicon design environmental factors. This design may over- or under-test SRAM cells for the target defects due to poor process tracking characteristics and may require multiple post-silicon design iterations to keep up with environmental changes following initial design. In the new circuit, multiple settings are designed in pre-silicon to account for the expected uncertainty in environmental factors. During post-silicon testing, a suitable stress setting is selected based on an acceptable or predetermined quality versus test yield tradeoff and its suitability is re-evaluated following any significant environmental changes to determine if a different stress setting is necessary.

Abstract: A new programmable weak write circuit is defined with the ability to perform SRAM weak write testing at multiple stress strength settings which track process variation. Prior art weak write test circuitry is designed to test a population of SRAM devices at a fixed weak write stress strength as determined by the best available pre-silicon design environmental factors. This design may over- or under-test SRAM cells for the target defects due to poor process tracking characteristics and may require multiple post-silicon design iterations to keep up with environmental changes following initial design. In the new circuit, multiple settings are designed in pre-silicon to account for the expected uncertainty in environmental factors. During post-silicon testing, a suitable stress setting is selected based on an acceptable or predetermined quality versus test yield tradeoff and its suitability is re-evaluated following any significant environmental changes to determine if a different stress setting is necessary.

Abstract: A processor includes a plurality of I/O connectors and an embedded memory array having a plurality of memory cells and a plurality of bitlines coupled to the plurality of memory cells. The processor also includes low yield analysis circuitry, coupled to both the embedded memory array and a first connector of the plurality of I/O connectors, to provide a coupling between a portion of the embedded memory array and the first connector.

Abstract: A method and apparatus for software controlled timing of embedded memory includes an embedded memory array and input/output (I/O) control circuitry coupled to the embedded memory array. The I/O control circuitry provides a plurality of I/O signals to the embedded memory array to control the input of data to the embedded memory array and output of data from the embedded memory array. The I/O control circuitry also includes programmable delay circuitry to alter the timing of the I/O signals.

Abstract: An apparatus includes an embedded memory, a plurality of input connectors to receive input signals from an external source, a plurality of output connectors to provide output signals to the external source, and a plurality of reconfigurable input and output signal paths coupled to the embedded memory and the plurality of input and output connectors. When the apparatus is operating in a first operating mode, the plurality of reconfigurable input and output signal paths provide the input signals directly to and the output signals directly from the embedded memory.

Abstract: A circuit for generating timing signals for operating an on-chip cache memory in which read operations of the cache memory occur in a first phase of a clock cycle and while operations occur in a second phase of the clock cycle and in which the operations to be accomplished in the second phase require a time for performance which may exceed the length of the second phase comprising means for generating the beginning of a write select signal as soon after the occurrence of both a write pulse and a hit signal as possible, and means for terminating the write select signal after a delay initiated by second phase of the clock cycle and termianted after a time sufficient to allow a write to take plate which time may actually extend into the next phase of the clock cycle.