Abstract: Synchronous timing techniques provide redundant reference frequencies to enable a packet switching system to continuously generate one or more master clock frequencies when an original reference frequency is lost or unavailable.

Abstract: Synchronous timing techniques provide redundant reference frequencies to enable a packet switching system to continuously generate one or more master clock frequencies when an original reference frequency is lost or unavailable.

Abstract: A phase delay compensator apparatus is provided which compensates for the phase error caused by propagation delay differences between clock and data paths within a computer system. A look-up table circuit is used to dynamically translate a change in frequency of the computer system clock or a change in the length of cable connecting the computer's sub-assemblies to a binary bit pattern defining the requisite phase-shift between distributed clock and data signals. A generator circuit produces phases of the phase-shifted clock signals, while ensuring the integrity of the loaded binary bit pattern. A gated signal is created for enabling the generator circuit.

Abstract: A method and apparatus for synchronizing two signals having a phase relationship and originating from transmission lines having unknown and differing skew includes a variable delay element with adjustable delay responsive to an applied biasing voltage inserted into one of the transmission lines. The phases of the signals are compared and phase error information generated. The error information is thereafter converted to a biasing voltage which is applied to the variable delay element. As a result, the delay characteristic of the one transmission line is adjusted to synchronize the signals.

Abstract: An electronically variable delay line having adjustable delay and bandwidth characteristics is provided. A varactor diode functioning as a variable controlled capacitance is coupled between a signal conductor and a ground reference conductor, thereby segmenting the signal conductor into two, individual smaller segments of conductor which function as fixed inductances. The delay characteristic of the line is adjusted by varying the varactor's biasing voltage which, in turn, varies the varactor's capacitance. A staggered termination technique is implemented to stabilize the insertion loss characteristics of the delay line.