Abstract: Devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment includes a die which has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have intentionally induced defects that form a predetermined fault pattern.

Abstract: Methods and devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment of the method includes fabricating a die, where the die has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have known defects that form a predetermined fault pattern at a predetermined location on the die. The bits are tested by using the logical addresses, wherein the testing yields data as to the functionality of the bits. The test results are searched for the predetermined fault pattern. The physical locations of the defective bits constituting the predetermined fault pattern are correlated with their logical addresses based on the location of the predetermined fault pattern.

Abstract: Methods and devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment of the method includes fabricating a die, where the die has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have known defects that form a predetermined fault pattern at a predetermined location on the die. The bits are tested by using the logical addresses, wherein the testing yields data as to the functionality of the bits. The test results are searched for the predetermined fault pattern. The physical locations of the defective bits constituting the predetermined fault pattern are correlated with their logical addresses based on the location of the predetermined fault pattern.

Abstract: An inductor integrated in a semiconductor device comprises a first and second lower electrical trace, an upper electrical trace, aligned at a first end with a first end of the first lower electrical trace and at a second end with a second end of the second lower electrical trace, a first via intercoupling the first end of the upper electrical trace with the first end of the first lower electrical trace, and a second via intercoupling the second end of the upper electrical trace with the second end of the second lower electrical trace.

Abstract: A fuse (50, 150, 200) with a low fusing current includes a first contact element (51, 151, 201) and a second contact element (51, 151, 201). A fusing element (53, 153, 203) is coupled between the first and second contact elements (51, 151, 201). At least a majority of the fusing element (53, 153, 203) comprises silicided material.

Abstract: A capacitor (110) having a bottom plate (104) that includes undoped polysilicon (106) which has been silicided (108). An advantage of the invention is providing a capacitor (110) having reduced parasitic capacitance to the substrate (100) and reduced sheet resistance of the bottom plate (104).

Abstract: A versatile system for reducing electromagnetic interference resulting from an inductor (300) formed within an integrated circuit is disclosed, including an inductor layer (310) having conductive elements (326) about its perimeter, first (306) and second (308) isolation layers disposed upon on opposite sides of the inductor layer and having conductive elements (326) about their perimeters, and first (302) and second (304) shield layers surrounding the first and second isolation layers, respectively, and coupled together by the conductive elements (326) of the isolation and inductor layers.

Abstract: A self-aligned silicide process with a selective etch of unreacted metal (plus any nitride) with respect to silicide plus a two step process of highly selective strip of unreacted metal (plus any nitride) followed by a silicide etch to remove unwanted silicide filament.

Abstract: A versatile system for reducing electromagnetic interference resulting from an inductor (300) formed within an integrated circuit is disclosed, including an inductor layer (310) having conductive elements (326) about its perimeter, first (306) and second (308) isolation layers disposed upon on opposite sides of the inductor layer and having conductive elements (326) about their perimeters, and first (302) and second (304) shield layers surrounding the first and second isolation layers, respectively, and coupled together by the conductive elements (326) of the isolation and inductor layers.

Abstract: A capacitor (110) having a bottom plate (104) that comprises undoped polysilicon (106) which has been silicided (108). An advantage of the invention is providing a capacitor (110) having reduced parasitic capacitance to the substrate (100) and reduced sheet resistance of the bottom plate (104).

Abstract: A fuse (50, 150, 200) with a low fusing current includes a first contact element (51, 151, 201) and a second contact element (51, 151, 201). A fusing element (53, 153, 203) is coupled between the first and second contact elements (51, 151, 201). At least a majority of the fusing element (53, 153, 203) comprises silicided material.

Abstract: An inductor integrated in a semiconductor device is disclosed, comprising a first and second lower electrical trace, an upper electrical trace, aligned at a first end with a first end of the first lower electrical trace and at a second end with a second end of the second lower electrical trace, a first via intercoupling the first end of the upper electrical trace with the first end of the first lower electrical trace, and a second via intercoupling the second end of the upper electrical trace with the second end of the second lower electrical trace.

Abstract: A capacitor (110) having a bottom plate (104) that comprises undoped polysilicon (106) which has been silicided (108). An advantage of the invention is providing a capacitor (110) having reduced parasitic capacitance to the substrate (100) and reduced sheet resistance of the bottom plate (104).

Abstract: The use of silicon carbide to form sidewall spacers allows the use of a lower temperature deposition step, and provides greater etch selectivity with respect to oxide.

Abstract: A strip for TiN with selectivity to TiSi2 consisting of a water solution of H2O2 with possible small amounts of NH4OH.

Abstract: A method of selectively forming porous silicon regions (106) in a silicon substrate (100). A masking layer (104) of SiC is deposited by PECVD over the substrate (100) using an organosilicon precursor gas such as trimethylsilane, silane/methane, or tetramethylsilane at a temperature between 200-500.degree. C. The masking layer (104) of SiC is then patterned and etched to expose the region of the substrate (100) where porous silicon is desired. An anodization process is performed to convert a region of the substrate to porous silicon (106). The SiC masking layer (104) withstands the HF electrolyte of the anodization process with little to no degradation.

Abstract: A self-aligned silicide method with Ti deposition, reaction, strip of TiN with selectivity to TiSi.sub.2 consisting of a water solution of H.sub.2 O.sub.2 with possible small amounts of NH.sub.4 OH, phase conversion anneal, and then strip of TiSi.sub.2 filaments with a water solution of H.sub.2 O.sub.2 plus NH.sub.4 OH.

Abstract: A polysilicon resistor (40) includes a field oxide layer (12) and a polysilicon layer (20) that covers a portion of field oxide layer (12). The polysilicon layer (20) possesses a predetermined electrical resistance value. Nitride/oxide stack (42) covers a predetermined portion of the polysilicon layer (20) and forms at least one exposed location of polysilicon layer (20) on which not to implant a dopant to achieve a predetermined resistance value. Silicide layer (34) covers exposed location.