Abstract: A technique for cloud infrastructure backup in a virtualized environment utilizing shared storage includes obtaining a workload input/output (I/O) profile to the shared storage over a time period. An attempt to locate one or more time windows in the workload I/O profile for which a cloud infrastructure backup can be staged is initiated. In response to determining the cloud infrastructure backup can be staged during at least one of the time windows, staging of the cloud infrastructure backup is scheduled during a selected one of the time windows. In response to determining the cloud infrastructure backup cannot be staged during at least one of the time windows, an interference tolerance approach is employed for accessing the shared storage for active workloads and the cloud infrastructure backup during the staging of the cloud infrastructure backup.

Abstract: A technique for cloud infrastructure backup in a virtualized environment utilizing shared storage includes obtaining a workload input/output (I/O) profile to the shared storage over a time period. An attempt to locate one or more time windows in the workload I/O profile for which a cloud infrastructure backup can be staged is initiated. In response to determining the cloud infrastructure backup can be staged during at least one of the time windows, staging of the cloud infrastructure backup is scheduled during a selected one of the time windows. In response to determining the cloud infrastructure backup cannot be staged during at least one of the time windows, an interference tolerance approach is employed for accessing the shared storage for active workloads and the cloud infrastructure backup during the staging of the cloud infrastructure backup.

Abstract: A technique for cloud infrastructure backup in a virtualized environment utilizing shared storage includes obtaining a workload input/output (I/O) profile to the shared storage over a time period. An attempt to locate one or more time windows in the workload I/O profile for which a cloud infrastructure backup can be staged is initiated. In response to determining the cloud infrastructure backup can be staged during at least one of the time windows, staging of the cloud infrastructure backup is scheduled during a selected one of the time windows. In response to determining the cloud infrastructure backup cannot be staged during at least one of the time windows, an interference tolerance approach is employed for accessing the shared storage for active workloads and the cloud infrastructure backup during the staging of the cloud infrastructure backup.

Abstract: A technique for cloud infrastructure backup in a virtualized environment utilizing shared storage includes obtaining a workload input/output (I/O) profile to the shared storage over a time period. An attempt to locate one or more time windows in the workload I/O profile for which a cloud infrastructure backup can be staged is initiated. In response to determining the cloud infrastructure backup can be staged during at least one of the time windows, staging of the cloud infrastructure backup is scheduled during a selected one of the time windows. In response to determining the cloud infrastructure backup cannot be staged during at least one of the time windows, an interference tolerance approach is employed for accessing the shared storage for active workloads and the cloud infrastructure backup during the staging of the cloud infrastructure backup.

Abstract: A system with a processor in communication with a memory controller in communication with a plurality of memory devices wherein one of the plurality of memory devices is interposed between the memory controller and the remaining plurality of memory devices. By programming command delay in the memory controller, the command delay coordinates the execution of the command signal across all memory devices. The processor provides control signals to the memory controller that, in response, decodes the control signals and determines the mode of operation of one or more of the memory devices. The processor is also in communication with storage media and stores data in or retrieves data from the storage media.

Abstract: A system with a processor in communication with a memory controller in communication with a plurality of memory devices wherein one of the plurality of memory devices is interposed between the memory controller and the remaining plurality of memory devices. By programming command delay in the memory controller, the command delay coordinates the execution of the command signal across all memory devices. The processor provides control signals to the memory controller that, in response, decodes the control signals and determines the mode of operation of one or more of the memory devices. The processor is also in communication with storage media and stores data in or retrieves data from the storage media.

Abstract: A daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the memory controller can effectively predict when a command sent by it will be executed by the addressee DIMM. By programming DIMM-specific command delay in the DIMM's command delay unit, the command delay balancing methodology according to the present disclosure “normalizes” or “synchronizes” the execution of the command signal across all DIMMs in the memory channel. By predicting command execution timing, the memory controller can efficiently control power profile of all the DRAM devices (or memory modules) on a daisy-chained memory channel. A separate DIMM-specific response delay unit in the DIMM is programmable to provide DIMM-specific delay compensation in the response path, further allowing the memory controller to accurately ascertain the timing of receipt of a response.

Abstract: A daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the memory controller can effectively predict when a command sent by it will be executed by the addressee DIMM. By programming DIMM-specific command delay in the DIMM's command delay unit, the command delay balancing methodology according to the present disclosure “normalizes” or “synchronizes” the execution of the command signal across all DIMMs in the memory channel. By predicting command execution timing, the memory controller can efficiently control power profile of all the DRAM devices (or memory modules) on a daisy-chained memory channel. A separate DIMM-specific response delay unit in the DIMM is programmeable to provide DIMM-specific delay compensation in the response path, further allowing the memory controller to accurately ascertain the timing of receipt of a response.

Abstract: A methodology for a daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the memory controller can effectively predict when a command sent by it will be executed by the addressee DIMM. By programming DIMM-specific command delay in the DIMM's command delay unit, the command delay balancing methodology according to the present disclosure “normalizes” or “synchronizes” the execution of the command signal across all DIMMs in the memory channel. With such ability to predict command execution timing, the memory controller can efficiently control power profile of all the DRAM devices (or memory modules) on a daisy-chained memory channel.

Abstract: A methodology for a daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the memory controller can effectively predict when a command sent by it will be executed by the addressee DIMM. By programming DIMM-specific command delay in the DIMM's command delay unit, the command delay balancing methodology according to the present disclosure “normalizes” or “synchronizes” the execution of the command signal across all DIMMs in the memory channel. With such ability to predict command execution timing, the memory controller can efficiently control power profile of all the DRAM devices (or memory modules) on a daisy-chained memory channel.

Abstract: A methodology for a daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the memory controller can effectively predict when a command sent by it will be executed by the addressee DIMM. By programming DIMM-specific command delay in the DIMM's command delay unit, the command delay balancing methodology according to the present disclosure “normalizes” or “synchronizes” the execution of the command signal across all DIMMs in the memory channel. With such ability to predict command execution timing, the memory controller can efficiently control power profile of all the DRAM devices (or memory modules) on a daisy-chained memory channel.

Abstract: A methodology for a daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the memory controller can effectively predict when a command sent by it will be executed by the addressee DIMM. By programming DIMM-specific command delay in the DIMM's command delay unit, the command delay balancing methodology according to the present disclosure “normalizes” or “synchronizes” the execution of the command signal across all DIMMs in the memory channel. With such ability to predict command execution timing, the memory controller can efficiently control power profile of all the DRAM devices (or memory modules) on a daisy-chained memory channel.

Abstract: A methodology for a daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the memory controller can effectively predict when a command sent by it will be executed by the addressee DIMM. By programming DIMM-specific command delay in the DIMM's command delay unit, the command delay balancing methodology according to the present disclosure “normalizes” or “synchronizes” the execution of the command signal across all DIMMs in the memory channel. With such ability to predict command execution timing, the memory controller can efficiently control power profile of all the DRAM devices (or memory modules) on a daisy-chained memory channel.

Abstract: A filter system for receiving an oil-in-water emulsion contaminated with an emulsified contaminant oil, and separating the emulsified contaminant oil from the oil-in-water emulsion includes a filter media for receiving the oil-in-water emulsion and emulsified contaminant oil, having an inner filter element formed from a 95 percent single pass efficiency 48 micron (5 micron nominal) filtering material of needle punch polypropylene felt, an outer filter element formed from a 95 percent single pass efficiency 19 micron absolute filtering material of a polypropylene microfiber material and a porous spunbond polypropylene sandwiching the outer filter media. The filter element de-emulsifies the emulsified contaminant oil from the oil-in-water emulsion into the contaminant oil and the oil-in-water emulsion, separates the de-emulsified contaminant oil from the oil-in-water emulsion, coalesces the separated contaminant oil and passes both the coalesced de-emulsified contaminant oil and the oil-in-water emulsion.

Abstract: A filter system for receiving an oil-in-water emulsion contaminated with an emulsified contaminant oil, and separating the emulsified contaminant oil from the oil-in-water emulsion includes a filter media for receiving the oil-in-water emulsion and emulsified contaminant oil, having an inner filter element formed from a 95 percent single pass efficiency 48 micron (5 micron nominal) filtering material of needle punch polypropylene felt, an outer filter element formed from a 95 percent single pass efficiency 19 micron absolute filtering material of a polypropylene microfiber material and a porous spunbond polypropylene sandwiching the outer filter media. The filter element de-emulsifies the emulsified contaminant oil from the oil-in-water emulsion into the contaminant oil and the oil-in-water emulsion, separates the de-emulsified contaminant oil from the oil-in-water emulsion, coalesces the separated contaminant oil and passes both the coalesced de-emulsified contaminant oil and the oil-in-water emulsion.

Abstract: A method for providing the results of an address decode operation involves comparing the address of an address to be decoded with the address range containing an address previously decoded in a previous address decode operation, selecting the results of the previous address decode operation if the address of an address to be decoded is within the address range containing an address previously decoded in a previous address decode operation, and decoding the address to be decoded in a current address decode operation and selecting the results of the current address decode operation if the address containing an address to be decoded is not within the address range of an address previously decoded in a previous address decode operation.

Abstract: An apparatus is described for controlling pipelined memory access requests in a computer system. A graphics controller is coupled with a system memory by an AGP interface, which has separate write and read request queues. To control the ordering of the write and read requests relative to one another, each of the requests has an associated age tag assigned to it. In the event a read request is received by the AGP interface, an age tag value is assigned to it that corresponds with the number of previously received and currently pending write requests. Similarly, when a write request is received by the AGP interface, an age tag value is assigned that corresponds with the number of previously received and currently pending read requests. Employing such age tags provides AGP-compliant ordering of the write and read requests, while also providing write-passing-read capability without the attendant complex logic circuitry and time delays associated with conventional implementations.

Abstract: A method is described for controlling pipelined memory access requests in an AGP-compliant computer system. Memory access requests are stored in separate write and read request queues. To control the ordering of the write and read requests relative to one another, each of the requests has an associated age tag assigned to it. In the event a read request is received, an age tag value is assigned to it that corresponds with the number of previously received and currently pending write requests. Similarly, when a write request is received, an age tag value is assigned that corresponds with the number of previously received and currently pending read requests. Employing such age tags provides AGP-compliant ordering of the write and read requests, while also providing write-passing-read capability without the attendant complex logic circuitry and time delays associated with conventional AGP implementations.

Abstract: A logic device has address decoding logic for receiving an address to be decoded, for performing address decode operations and for providing current address decode operation results, an address range register for storing the address range of a previously decoded address, address comparing logic for comparing the address of the address to be decoded and the address range of the previously decoded address and selecting logic for bypassing a current address decode operation if the address of the address to be decoded is within the address range of the previously decoded address. The device may further have an address decode results register for storing the results of a previous address decode operation, wherein the selecting logic selects the results of the previous address decode operation stored in the address decode results register if the current address decode operation is bypassed.